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基于FPGA的直接数字频率合成器（DDS）设计
- 基于FPGA的直接数字频率合成器（DDS）设计 （源程序）,FPGA-based direct digital synthesizer (DDS) design (source code)
accumulator.rar
- 实现累加器的verilog源码，广泛应用在通信电路设计中,The realization of accumulator Verilog source, widely used in communication circuit design
EDA.rar
- 这里边有EDA设计常用模块的源代码，FFT,DDS PS2_keyboard，VGA等，有学FPGA的就参考一下吧,Here the design of commonly used modules have EDA source code, FFT, DDS PS2_keyboard, VGA and so on, have places on the FPGA reference yourself
cordicDDS
- Cordic算法实现DDS的Verilog 源码,14位精度，非常实用的。-DDS algorithm Cordic the Verilog source code, 14-bit accuracy, very practical.
FPGA-DDS
- 在FPGA内，以查表方式实现频率直接合成器（DDS）功能。verilog源代码-In the FPGA in order to achieve the look-up table means the direct synthesizer frequency (DDS) feature. verilog source code
dds_verilog
- 产生信号发生器的dds的verilog代码，很好的学习资料，值得学习-Verilog code generated signal generator dds good learning materials, it is worth learning
DDS
- this a code for DDS in Verilog-this is a code for DDS in Verilog
DDSVerilog
- DDS Verilog 代码。包含英文文档说明-DDS Verilog code. Containing the English documentation
DDS
- DDS数字频率合成的verilog代码，附有正余弦查找表等-DDS digital frequency synthesis verilog code, with a cosine look-up table, etc.
ddsfinal1
- verilog语言实现的dds代码，并行通信，生成四种波形，大赛编写的代码，modelsim仿真-verilog language dds code,modelsim debug
DDS
- 关于用FPGA制作的DDS源代码。用的是verilog语言，用的是xlinx的软件-Produced with the DDS on FPGA source code. Using verilog language, using xlinx software
dds_quicklogic
- dds 源代码 verilog 很有意义-dds dds verilog source code makes sense
DDS-in-Verilog
- Verilog编写基于FPGA的DDS实现，内含源代码，希望对大家有所帮助。-DDS in Verilog FPGA-based implementation, including source code, we want to help.
DDS-VERILOG
- DDS的信号发生器verilog代码 可直接用于编程 已经测试-Verilog code of the DDS signal generator which can be used directly in the programming has been tested
dds
- 使用AD5559,结合quartus中的硬件描述语言,实现了雷达发射信号二相码信号-using AD9959 and combining with verilog to output a rada signal of Binary code
DDS-frequency-synthesizer
- 本文主要讨论了Verilog语言的基于DDS的波形发生器的设计。从设计要求入手，本文给出了DDS的详细设计过程，包括各个模块的设计思想，电路图，Verilog语言程序代码。其大致思想为通过频率控制字和相位控制字去控制正弦函数的ROM存储表的地址并对应着得到其幅度值，最终达到输出需要波形的目的。-This paper mainly discusses the design of the Verilog language, the DDS-based waveform generator. Star
DDS
- 基于verilog的DDS设计验证与仿真源代码，在quartus上实现，下载仿真成功-Based on the the the verilog DDS design verification and simulation of the source code, in quartus download simulation success
dds
- 采用硬件描述语言verilog进行DDS变换的实现的代码-Using hardware descr iption languages Verilog implementation of DDS converter code
DDS
- 基于fpga的正余弦波形发生器，Verilog代码，测试通过。-Cosine waveform generator fpga based, Verilog code, the test passes.
DDS
- 描述了verilog实现的DDS信号发生器，可以经过FPGA验证，包括了代码实现以及书写。代码可以经过altera的EDA工具进行了验证，可以实现信号发生器的基本功能。希望大家珍惜，并好好学习。(Describes the Verilog implementation of the DDS signal generator, which can be verified by FPGA, including code implementation and writing. Code can be