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DE2_70_pin_assignments.rar
- de2-70的引脚配置文件，给各位急需分享一下，用于fpga的开发,de2-70 of the pin configuration files, to share that much-needed for the development of fpga
DE2_pin_assignments
- altera DE2开发板的管脚配置文件很好用的哦-altera DE2 development board of the pin configuration files used by Oh well
LEDtest
- 简单的7段数码管驱动，对应de2，可直接用，内含de2板子的管脚分配-Simple digital control driver 7, corresponding to de2, can be directly used, containing de2 board pin allocation
DE2usingbook
- DE2中文用户手册，方便查找各引脚所对的编码-DE2 Chinese user manual, easy to find the pin that on the coding
DE2jieshao
- DE2中文用户手册。对de2板的各个模块的一些介绍和管脚图-DE2 Chinese user manual. De2 board of some descr iption of each module and the pin map
DE2EP2C35F672
- DE2 EP2C35F672d的管脚分配图-DE2 EP2C35F672d pin allocation map
codelock7(0)
- Altera的DE2板子的一个简易密码锁，引脚信号已经引入，在实验板上调试通过-Altera' s DE2 board a simple password lock pin has been introduced by the experimental board debugging
lab1
- 本实验主要练习使用Quartus II 9.1软件进行简单的FPGA 的I/O口实验，实验使用的是DE2开发板，使用芯片为EP2C35F672C6。本次实验的重点是掌握Quartus II 进行系统设计的流程、方法及调试技巧，并对DE2开发板的各个引脚的含义及使用有所了解。-This experiment and practice using the Quartus II 9.1 software is a simple FPGA' s I/O port experiments using
DE2-VGA-LED
- verilog HDL 语言编写的，FPGA的数码管和VGA的显示。调用时不必修改源码，只需引脚映射对就可以-verilog HDL language, FPGA digital and VGA display. Call without having to modify source code, you can just pin on the map
DE2_pin_assignments
- DE2_pin_assignments DE2开发板引脚设置-DE2_pin_assignments DE2 development board pin
SEG7
- ALTERA公司DE2开发板的数码管驱动程序，包含引脚配置文件-ALTERA DE2 board digital driver contains the pin configuration files
DE2_115_PS2_DEMO
- DE2-115开发板上的PS2针口程序，VHDL语言开发，QT2环境下可调式-PS2 pin port program the DE2-115 development board, VHDL language development, QT1 environment adjustable
DE2_NIOS
- DE2 板子的范例 内涵引脚连接示范硬件配置和大量常用IP CORE 非常适合新手学习研究-Example content of the DE2 board demonstration hardware configuration and a large number of commonly used IP CORE pin is ideal for the novice to learn research
DE2_70_pin_assignments
- DE2-70开发板中附带的引脚的分配列表，格式为.csv的-DE2-70 development board comes with the pin assignment list, in the format. Csv
frequency-counter
- 这是用verilog写的配合DE2 FPGA开发板的10进制显示频率计的工程文件夹的压缩包，解压后可直接下载到DE2板上，其中频率输入端是系统自带27M时钟D13用于测试，如果想要应用于别的开发板，可以重新分配引脚。-DE2 FPGA development board with with verilog write with decimal display frequency meter project folder compression package, after decompressi
SDRAM
- DE2 SDRAM Controller Pin Configuration Set-DE2 SDRAM Controller Pin Configuration Set!!!
DM9000A_IF
- DE2平台上对DM9000A进行管脚配置的vhdl程序。-DE2 platform on the pin configuration of the VHDL program on DM9000A
EP2C70F896C6N-pins
- 将VHDL程序下载到DE2开发板，引脚分配时需要知道的芯片每个引脚功能-VHDL program will be downloaded to the DE2 development board, you need to know when the pin assignments for each pin of the chip functions
Quartus_FPGA
- this a smal programme that convert a binary code to a gray code, and a file that expalin the DE2 pin assignements-this is a smal programme that convert a binary code to a gray code, and a file that expalin the DE2 pin assignements
DE2-115引脚分配
- DE2-115引脚分配说明，使用时查找十分方便。(DE2-115 pin assignment descr iption)