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i2c_master_slave_core
- I2C master/slave IP core
i2c
- i2c master controller, free ip
I2C_code
- 与IP核配套的I2C-Master Core，包含了目前主流FPGA芯片的I2C实现，代码包括Altera/Xilinx/OpenCore等公司的VHDL/Verilog/C等。-I2C-Master Core
RD1054
- i2c接口的master ip 适用于lattice的器件-i2c master ip interface device for lattice
i2c_master
- I2C master模式的IP core（verilog）-I2C master mode IP core (verilog)
i2c
- I2C master mode IP core
i2c_core
- i2c ip core support slave and master mode
i2c_verilog
- I2C Master IP 核 I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. It is most suitable for applications requiring occasional communication over a short distance between
i2c_master_slave_core
- I2C接口的主从模式代码,独立的IP，可以快速嵌入到自己的设计项目！-Master I2C interface code from the model, independent of IP, you can quickly embed into their design projects!
i2c-master
- i2c 总线 host 控制器 ， fpga上验证过，可以实现i2c 通信。-verilog IP for i2c master controller
i2c_master_ip_for_nios
- i2c master ip for altera nios, add in qsys
i2c design ware用户手册
- 新思科技DW IP i2c 可配置master和slave i2c协议