搜索资源列表
Phase Locked Loop.mdl
- Phase Locked Loop model for matlab
pll.rar
- 模拟锁相环（apll）的一些simulink模型,Analog phase-locked loop (apll) some simulink model
verilog
- 采用用verilog语言编写的全数字锁相环的源代码。-Verilog language used by all-digital phase-locked loop' s source code.
MC145152
- 1、数字锁相环的单片机代码。 2、单片机与数字锁相环MC145152的应用系统的设计与实现。-1, the single-chip digital phase-locked loop code. 2, microcontroller and digital PLL MC145152 Application System Design and Implementation.
pll
- 一個基本的鎖相迴路設計(PLL)simulink 程序-A basic phase-locked loop design (PLL) simulink program
PLL
- PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上； 顶层文件是PLL.GDF-Digital phase-locked loop PLL is the design source code, which, Fi is the input frequency (receive data), Fo (Q5) is
phase-locked
- 主要是关于锁相环的环路滤波设计与计算，非常经典的-Mainly on the phase-locked loop filter design and calculation, very classic
PLL
- 锁相环问题的仿真，可以解决数字锁相环的仿真问题-Phase-locked loop simulation problem, can solve the problem of digital phase-locked loop simulation
PhaseLockedLoop
- This tutorial starts with a simple conceptual model of an analog Phase-Locked Loop (PLL). Through elaboration it ends at a model of an all digital and fixed-point phase-locked loop. The final model can serve a starting point for code generation (both
pll_ok
- 完整的锁相环matlab代码实现，其中包括高斯噪声干扰，频差，相差，给出最后频率及相位收敛结果图。重要的是代码中有本人详细注释，易于理解-Complete phase-locked loop matlab code, including the Gaussian noise interference, frequency difference, a difference, given the final results of the frequency and phase diagram con
Matlabpll
- 基于Matlab的数字锁相环的仿真设计，一篇毕业论文，对数字和模拟锁相环进行了详细的分析和仿真-Matlab-based simulation of digital PLL design, a thesis on digital and analog phase-locked loop for a detailed analysis and simulation
PLL
- Phase locked loop(PLL) Verilog HDL code
Phase-locked-loop
- 该程序是锁相环的MATLAB的简单实现程序，从中可以看到锁相环的基本功能的实现。-This program is a simple phase locked loop of MATLAB implement programs, from which you can see the basic function of phase-locked loop of implementation.
Phase-Locked-Loop.rar
- charge pump phase-locked loop with digital phase-frequency detector,charge pump phase-locked loop with digital phase-frequency detector matalab model
Phase-Locked-Loop
- matlab code for Phase Locked Loop tutorial
phase-locked-loop-implementation
- 在FM0数据解码时，利用锁相环生成数据同步时钟信号。文件为锁相环实现。Verilog HDL-When FM0 decoding data using the phase-locked loop generates the data synchronizing clock signal. File for phase-locked loop implementation.Verilog HDL
Phase-locked-loop
- 用于解决单相并网中的锁相环问题，并实现相应的仿真验证探究。-To solve the problem of single phase grid connected in phase locked loop
All-Digital-Phase-Locked-Loop-Design-and-Implemen
- All Digital Phase Locked Loop Design and Implementation
Phase-Locked-Loop
- phase locked loop for the phase angle calculations required in control system and power system. it gives phase and frequency of the input signal.
Phase Locked Loop
- 锁相环matlab仿真模拟代码，通过相位实现调控(Phase locked loop matlab simulation code, control by phase)