搜索资源列表
16bit-CLA
- 16 bit carry look ahead adder verilog code
cla4
- verilog code 4-bit carry look-ahead adder output [3:0] s //summation output cout //carryout input [3:0] i1 //input1 input [3:0] i2 //input2 input c0 //前一級進位-verilog code4-bit carry look-ahead adderoutput [3:0] s// summationoutput cout// c
cla16
- verilog code 16-bit carry look-ahead adder output [15:0] sum // 相加總和 output carryout // 進位 input [15:0] A_in // 輸入A input [15:0] B_in // 輸入B input carryin // 第一級進位 C0 -verilog code16-bit carry look-ahead adderoutput [15:0] sum// sum of
16bitCLA
- 基于Verilog HDL的16位超前进位加法器 分为3个功能子模块-Verilog HDL-based 16-bit CLA is divided into three functional sub-modules
lookahead
- implement of carry look ahead adder vith verilog
CarryLookAheadAdder
- Carry Look Ahead Example with VHDL code. Good code for altera platform
sumadores
- Carry look ahead, sumador con acarreo de 32 bits
lab5_2
- this a vhdl project on 4-bit multiplier with carry look ahead implementation and 8-bit result -this is a vhdl project on 4-bit multiplier with carry look ahead implementation and 8-bit result
CLAAdd
- This zip folder contains the Carry look ahead in verilog HDL
32bitcarrylookaheadadder
- 32位超前进位加法器的源代码和testbench-32 bit carry look ahead adder and its testbench
add8
- carry look ahead 8 bit adder
Advanced_Adders
- Advanced topic on adders including: Carry Look Ahead Adder, Binary Parallel Adder/Subtractor, BCD adder circuit, Binary mutiplier circuit.
CLA4
- Carry look Ahead Adder using top level
16bit-CLA
- a 16 bit carry look ahead adder verilog code
CLA
- carry look ahead adder
VHDL-ripple-lookahead-carryselect-adder
- vhdl code for ripple carry adder, carry select adder and carry look ahead adder
4_Bit_CLA_4.0.vhd
- 4-Bit Carry Look Ahead adder
adder1
- adder Ripple Carry Adder(RCA) Carry Look-ahead Adder(CLA) Block Ripple Carry Adder(BRCA) Two-Level Carry Look-ahead Adder-Ripple Carry Adder(RCA) Carry Look-ahead Adder(CLA) Block Ripple
carry-look-ahead-adder32
- This implements Carry look ahead adder in verilog
carry-look-ahead
- it's implementation for carry lookahead adder in vhdl