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fdpll
- 简单的可配置dpll的VHDL代码。 用于时钟恢复后的相位抖动的滤波有很好的效果， 而且可以参数化配置pll的级数。-simple configurable dpll VHDL code. Clock Recovery for the jitter filtering is a very good result, but can pll configuration parameters of the series.
Jitter
- The code summerize how to calculate the jitter (RMS) with the incoming signals, such as optical communications and clock and date recovery circuit
5B6B
- FPGA的5B6B编译码器的设计代码可以编译而且有波形图 -5B6B code is used in fiber optic digital communication systems a more extensive line pattern! Data are 5B6B encoding and conversion, and string after the fiber transmission, serial code sequences in continuous bit 0 or b
Design_of_a_6.25_Gbps_Backplane_SerDes_with_TOP-do
- SerDes自顶向下的设计方法流程，包括接收机、发射机、均衡技术、时钟恢复技术-SerDes top-down design methodology process, including receivers, transmitters, equalization, clock recovery techniques
shift
- E1接收部分主要功能是实现从输入的差分线路数据中恢复出2.048M线路时钟并将数据解码输出。包括解码和线路时钟恢复两模块。-E1 to receive some of the major functions of the difference from the input data lines to recover a clock and data lines 2.048M decoder output. Including decoding and clock recovery circuit
5b6b
- 5B6B码是光纤数字通信系统中使用比较广泛的一种线路码型! 数据经过5B6B编码和并串转换后在光纤上传输，串行码序列中连续的比特0或比特1的长度不超过5，数据在0和1之间变换的密度很高,并具有直流平衡的特性，有利于接收电路和时钟恢复电路的设计。-5B6B code is used in fiber optic digital communication systems a more extensive line pattern! Data are 5B6B encoding and conver
SERDES
- 基于Verilog的串并转换器的设计与实现，采用两种不同的方案来实现串并和并串转换的功能，并用ISE软件仿真以及chipscope的调试-Verilog-based serial and parallel converter design and implementation of two different programs to achieve the string and and and string conversion functions, and use the ISE softwa
work12
- zlg7290和I2C控制PIC单片机实现实时时钟的功能，时钟可调，断电存储，上电恢复时间！-zlg7290 and PIC microcontroller I2C control functions for real-time clock, clock adjustable, power storage, power recovery time!
APL99
- An All-Digital Phase-Locked Loop (ADPLL)-Based Clock Recovery
xapp250
- xilinx 关于时钟数据恢复中的源代码-xilinx on the clock and data recovery in the source code
pll_clock
- 自己写的时钟提取逻辑。用于时钟恢复电路。-Write your own clock extraction logic. For the clock recovery circuit.
OFDM_retiming
- 基于Verilog的OFDM时钟恢复模块，在做全数字OFDM的时候是关键模块，可以在FPGA上实现。-Verilog-OFDM-based clock recovery module, doing all-digital OFDM time is the key module can be implemented on the FPGA.
Up_timingBYM
- A timing error detector for Communication systems with simulink. # Required versions Matlab 5.2.1, Simulink 2.2.1 # File descr iption 1. ti_det1.m (simulink version 5.2.1) An s-function to be used for timing detector. For detailed i
sfdppllli
- 简单易懂的可配置dpll的VHDL代码。用于时钟恢复后的相位抖动的的滤波有非常好的效果， 而且能参数化配置pll的级数。 已通过测试。 -Straightforward configuration VHDL code dpll. Very good results for the clock recovery phase jitter filtering, and can be parameterized configuration pll series. Has been tested.
LMH0346
- 国家半导体的时钟恢复芯片LHM0346，双差分-National Semiconductor Clock Recovery Chip LHM0346
clcRec
- This a clock recovery matlab code. This file is using a 4-PAM signal shape and the recovery method is DD recovery method. This file is a mfile. -This is a clock recovery matlab code. This file is using a 4-PAM signal shape and the recovery method i
clcRecoveryDDmethod
- this file is implementing CLOCK recovery using DD method in matlab. This is a mfile. The signal shape is 4PAM
cdr
- 数据时钟恢复，采样8倍率高频时钟进行数据时钟恢复。已通过Modelsim仿真-Data and clock recovery, sampling 8 times the rate of high frequency clock for clock and data recovery. Have been through the Modelsim simulation
scc
- experimental fullduplex mode with DPLL BRG for MODEMs without clock recovery. -experimental fullduplex mode with DPLL BRG for MODEMs without clock recovery.
Freq_Synthesis_1p0
- PLL的模型，包括连续型与离散型。包括分数分频，双模式，SERDES时钟恢复。-This is a collection of PLL modeling examples, both continuous and discrete time. It includes integer as well as fractional N, dual modulus, SERDES clock recovery.