搜索资源列表
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verilog code for counter four
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关于FPGA实现的几种计数器的verilog源程序-FPGA implementation of several counter verilog source code
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8-Bit Up Down Counter Verilog Code
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计数器Verilog源程序，可轻易实现数目的计算，包含源程序及实现方法。-Counter Verilog source code, the number of calculations can be easily achieved, including source code, and Realization.
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一种计数器的FPGA的verilog源程序和仿真图谱-A kind of counter verilog source code and simulation of FPGA-map
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this is a verilog code for asynchronous mod-10 counter.its also called a decade counter.
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System watchdog verilog code
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counter verilog code
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基于verilog的计时器源代码，可以通过编译-Verilog source code based on the timer, you can compile
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Custom verilog code for up counter with Interrupt.
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这是可变模加减计数器的Verilog源程序，已经编译通过，可以使用-This is the variable mode subtraction counter Verilog source code, has been compiled by, you can use
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counter.v...its verilog code for counter
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用VERILOG语言实现的74*163 计数器，代码十分简单易懂，适合数字逻辑电路实验的初学者-With the VERILOG language implementation of the 74* 163 counter, the code is very simple and easy to understand, suitable for digital logic circuit experiment for beginners
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Verilog代码：同步\异步FIFO。包含格雷码计数器.-Verilog code: syncronous\asyncourous FIFO. containing gray counter.
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the file contains verilog code for johnson counter
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verilog code for mod13 counter source code-verilog code for mod13 counter source code
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Ring counter souce code in verilog
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计数器实现的verilog代码，基础的实用，大家多多支持-Counter verilog code to achieve, based on practical, we can support
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Gray counter verilog code
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Binary counter design in verilog
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