搜索资源列表
ModelSim6c_SE_Cracker
- crack for ModelSim, a Verilog, VHDL and mixed VHDL / Verilog CAD simulator for FPGA, board and IC design.-crack for ModelSim, a Verilog. VHDL and mixed VHDL / Verilog simulator for CAD F PGA, board and IC design.
ps2_vhdl
- 利用vhdl实现FPGA芯片从PS2键盘读出数据(0-F) 并在数码管上显示 -use FPGA chip from the PS2 keyboard sensed data (0-F) and displayed on a digital control
01
- FPGA实现FFT算法 F PGA实现FFT算法
shuma
- 7段数码是纯组合电路，通常的小规模专用IC，如74或4000系列的器件只能作十进制BCD码译码，然而数字系统中的数据处理和运算都是2进制的，所以输出表达都是16进制的，为了满足16进制数的译码显示，最方便的方法就是利用VHDL译码程序在FPGA或CPLD中实现。本项实验很容易实现这一目的。例6-1作为7段BCD码译码器的设计，输出信号LED7S的7位分别接如图6-1数码管的7个段，高位在左，低位在右。例如当LED7S输出为 \"1101101\" 时，数码管的7个段：g、f、e、d、c、b、a分
altera_fft
- alter官方fft程序 使用verilog编写 需要的同学可以下载-alter the official fft program uses verilog prepared students in need can be downloaded
Mars-SP3-U_FPGA_manual
- Mars-SP3-U FPGA开发板说明，针对Xilinx的XC3S400，有对原理图的说明和实例操作说明-Mars-SP3-U FPGA development board that Xilinx for the XC3S400, there is schematic diagram of the descr iption and examples of instructions
niosII_cyclone_1c20
- IIR、F FT各模块程序设计例程，可做为IP使用，初学者很有用-IIR, FIR, FFT modular design of the routines can be used as IP use, useful for beginners
FPQ
- 基于FPGA的数控分频器，可以吧一个时钟信号分成不同频率的时钟信号。-FPGA-based digital frequency divider, a clock signal can now be divided into different frequency clock signals.
4
- 基于FPGA的FIR数字滤波器的设计与实现,基于FPGA的FIR数字滤波器的设计与实现-FPGA-based FIR digital filter design and implementation of FPGA-Based FIR Digital Filter Design and Implementation
reload_fir
- 这是我在Xilinx公司的FPGA上实现的FIR滤波器，调用的内部核，其特色是可以用较少的资源实现该功能，而且可以实现参数重载，即从外部MCU设置FIR滤波器的参数-This is my Xilinx FPGA to achieve the FIR filter, called internal audit, its characteristics can be achieved with fewer resources to this function, and the overload p
WCDMA-Frequency-Domain-Interference-Cancellation-f
- WCDMA数字频域干扰抵消器，绝对的高手写的文档和代码，里面资料齐全方便自学，是很好的学习FPGA实现无线通信模块的资料。-WCDMA Frequency Domain Interference Cancellation figures, the absolute master of written documentation and code, which complete information to facilitate self-learning, is a very good lea
f
- 为了解决传统的维特比译码器结构复杂、译码速度慢、消耗资源大的问题，提出一种新型的适用于FPGA特点，路径存储与译码输出并行工作，同步存储路径矢量和状态矢量的译码器设计方案。该设计方案通过仿真验证，译码结果正确，得到编码前的原始码元，速度显著提高，译码器复杂程度明显降低,性能优良。-The convolution code
FPGA-DISPLAY-0_F
- FPGA 开发板试验例程，在数码管实现0-F的显示-FPGA development board test routines in the digital display tube 0-F
PS2键盘实验－识别0-9和A-F 数码管显示值
- VHDL FPGA驱动键盘工程及源代码 试验已经通过 直接下载使用-VHDL FPGA driven keyboard Engineering and source code test has been used through direct download
A-compact-AES-core-with-on-line-error-detection-f
- This paper presents a compact, low-cost, on-line error-detection architecture for a 32-bit hardware implementation of the AES. The implemented AES is specially designed for FPGA-based embedded applications, since it is tuned to specific FPGA logi
dr6—ise-F
- 用FPGA开发板的按键作为电子表的时间初值设置控制信号，数码管当前时间值输出。用按键选择分别输出：分、秒、1/10秒。(With FPGA development board button, as the time value of the electronic table, set the control signal, digital tube current time value output. Select output by buttons: minutes, seconds, and
Desktop
- fghfgvn fghfh rty fhfrt rt f ft
VGA_display_picture
- 实 现 基 于 f p g a 的 图 像 处 理(Realization of image processing based on FPGA)
茶叶茶艺茶道茶文化PPT模板
- 现在已知： 1)A美国人是医生。 2)E和俄罗斯人是技师。 3)C和德国人是技师。 4)B和f曾经当过兵，而德国人从未参过军。 5)法国人比A年龄大；意大利人比C年龄大。 6)B同美国人下周要去西安旅行，而C同法国人下周要去杭州度假。(Now it's known: 1) A American is a doctor. 2) E and the Russians are technicians. 3) C and the Germans are technicians. 4) B and f h
电路实验
- 实验一四位拨码开关控制显示数字0000~FFFF 实验二拨码开关控制数字0~F循环显示 实验三二位数码管循环显示数字00~FF 实验四二位数码管循环显示数字00~99(Experiment 1 Four-bit Dial Switch Control Display Digital 0000~FFFF Digital 0~F Cyclic Display Controlled by Experiment 2 Dial Switch Cyclic Display Digital 00~F