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verilog dpll（数字锁相环）
- 用xilinx ise 10.1实现了数字锁相环，仅供参考
典型实例10.8 字符LCD接口的设计与实现
- 典型实例10.8 字符LCD接口的设计与实现 软件开发环境：ISE 7.1i 硬件开发环境：红色飓风II代－Xilinx版 1. 本实例控制开发板上面的LCD的显示； 2. 工程在\project文件夹里面 3. 源文件和管脚分配在\rtl文件夹里面 4. 下载文件在\download文件夹里面,.mcs为PROM模式下载文件,.bit为JTAG调试下载文件。,Typical examples of character LCD interface 10.8 The Des
ISE7.1
- ise 中文使用手册，详细介绍如何使用ise，附大量图片说明-ise Chinese user manual details how to use the ise, attached to a large number of captions
tutorial
- 计数器 平台：Xilinx ise 10.1 说明：和ise10.1快速帮助手册配套的源码，适用于初学者。-counter platform: Xilinx ise 10.1 comment: supplement to ise quick start tutorial 10.1, suitable for freshman to fpga and ise software.
s3esk_startup
- 利用kcpsm3控制lcd显示 平台：ise 10.1， picoblaze， Spartan3e 开发板 说明：综合按键和lcd、led的功能，思想简单，需要新技术，适合想在fpga方面深造的人。-using kcpsm3 for lcd display platform: ise 10.1， picoblaze， Spartan-3E FPGA Starter Kit Board comment: involve lcd/led/switch, simple mind bu
adc2
- ADC control in VHDL language. Spartan 3E starter pack ISE 10.1
MD_DDS_10bit_VHDL
- 十位DA输出的DDS，用VHDL实现，环境：ISE 8.1，仿真软件：ModelSim_SE_6.1b-10 DA output of the DDS, with the VHDL implementation, environment: ISE 8.1, simulation software: ModelSim_SE_6.1b
paodan101
- 北京市电子设计大赛 完整工程 ISE10.1-ISE 10.1
vvTutorialonXilinxISE10.1
- EGR426 W’09 Laboratory #1 Tutorial on Xilinx ISE 10.1-EGR426 W’09 Laboratory#1 Tutorial on Xilinx ISE 10.1
IS61WV51216BLL
- 备注：使用的是VeriLog HDL语言 软件环境xilinx ISE 10.1，硬件：高教仪EXCD-1FPGA电路板。FPGA信号：spartan-3e . 功能编写硬件描述性语言实现FPGA对板上外设SRAM IS61WV51216BLL的读写，通过串口发送到上位机上，使用串口助手显示读取的数据。-Note: Use the VeriLog HDL language software environment xilinx ISE 10.1, hardware: Higher M
data_check_hand_in
- 一个基于状态机的8位码流检测实现，Verilog语言，在ISE 10.1环境下编译通过。-A state machine-based 8-bit code stream detection to achieve, Verilog language, the ISE 10.1 environment compile.
lab_instructions1
- The objective of the labs today is to give you a basic understanding of FPGA design and enough experience to begin your own FPGA design with the ISE 10.1 tools and the Xilinx Spartan-3A DSP 1800A Starter Kit.-The objective of the labs today is
lab_instructions2
- The objective of the labs today is to give you a basic understanding of FPGA design and enough experience to begin your own FPGA design with the ISE 10.1 tools and the Xilinx Spartan-3A DSP 1800A Starter Kit.-The objective of the labs today is
lab_instructions3
- The objective of the labs today is to give you a basic understanding of FPGA design and enough experience to begin your own FPGA design with the ISE 10.1 tools and the Xilinx Spartan-3A DSP 1800A Starter Kit.-The objective of the labs today is
Spartan-3ADSPs
- The objective of the labs today is to give you a basic understanding of FPGA design and enough experience to begin your own FPGA design with the ISE 10.1 tools and the Xilinx Spartan-3A DSP 1800A Starter Kit.-The objective of the labs today is
50973937-VHDL-Report
- Introduction This report is organized as following.First, it is divided into chapter 2 to chapter 12. Within each chapter, VHDL code is presented at the beginning of each problem. Then, simulation results for these codes is also included. For s
XILINX-ISE-MODELSIN-SE-Simulation
- Modelsim 10.0a 中建立 Xilinx ISE 13.1的仿真库及其之间调用设置详解。-Modelsim 10.0a create Xilinx 13.1 calls between the simulation library and its setting Detailed.
ISE-10.1-Quick-Start-Tutorial
- ISE10.1的快速入门手册，内有详细的快速上手开发示例-ISE10.1 Quick Start Guide, with detailed examples of the rapid development to get started
ISE-10.1-In-Depth-Tutorial
- 针对ISE10.1快速入门手册的近一步深化的说明手册，对更多更深入的功能进行了介绍和示例-Quick Start Manual for ISE10.1 taking a step forward to deepen the instruction manual for more in-depth features for more descr iption and examples were
Xilinx-ISE-10.1-Quick-Start-Tutorial
- VHDL Xilinx ISE 10.1 Quick Start Tutorial