高级链路层协议的实现，vhdl，fpga,- 8 bit parallel backend interface - use external RX and TX clocks - Start and end of frame pattern generation - Start and end of frame pattern checking - Idle pattern generation and detection (all ones) - Idle pattern

crc16的串行和并行写法，而且有详细的测试文件-Serial and parallel crc16 written, and detailed test documents

CCITT Parallel CRC 16-bit

包含16位CRC的并行实现和串行实现，并有测试程序。-Includes 16-bit CRC of the parallel and serial implementation to achieve, and test procedures.

用软件实现CRC校验码计算很难满足高速数据通信的要求， 基于硬件的实现方法中， 有串行经典算法LFSR,电路以及由软件算法推导出来的其它各种并行计算方法。以经典的LFSR,电路为基础， 研究了按字节并行计算CRC校验码的原理.-Implemented in software CRC checksum calculation is difficult to meet the requirements of high-speed data communications, hardware-based