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CORDIC_ip
- cordic IP core Features Each file is stand-alone and represents a specific configuration. The 4 parameters are: Rotation or Vector Mode Vector Precision Angle Precision Number of Cordic Stages All designs are pipelined
CORDIC
- ：CORDIC算法将复杂的算术运算转化为简单的加法和移位操作，然后逐次逼近结果。这种方法很好的兼顾了精度、速度和硬件复杂度，它与VLSI技术的结合对DSP算法的硬件实现具有极大的意义，因而在数字信号处理领域得到了广泛应用。本文首先简要介绍了CORDIC算法的原理，然后详细描述了双模式（旋转/向量）CORDIC算法的预处理和后处理，并且基于FPGA实现了流水线双模CORDIC算法。-By converting complex arithmetic into simple operations su
cordpipe
- pipelined cordic algorithm in hdl
69963930CORDIC
- cordic的fpga实现，基于verilog硬件语言实现，实现高速流水线的CORDIC。-cordic fpga implementation, hardware-based verilog language, to achieve high-speed pipelined CORDIC.
CORDIC
- pipelined CORDIC in structural model that contains 16 stages
cordicmaster
- cordic code algorithm using vhdl
dds_cordic
- 这是我自己编的一个基于流水线结构CORDIC算法实现DDS，32位的频率控制字的输入，CORDIC算法的迭代次数为15次。-This is my own DDS based on series of the pipelined CORDIC algorithm， a frequency control word：32 bit .The number of CORDIC iterations for the 15 time。
cordic
- verilog编写的数字信号发生器NCO用CORDIC方法实现产生sin cos信号，流水线结构，简单实用。-verilog prepared by the digital signal generator NCO using CORDIC method implementation generate sin cos signal, pipelined architecture, simple and practical。