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The file included is the source code for Pseudo Random Generator
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伪随机二进制序列发生器的Verilog源码，带测试文件，并在FPGA开发板上成功验证-Pseudo-random binary sequence generator Verilog source code, with a test file, and successfully verified in FPGA development board
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本次例程包括七阶伪随机序列发生器、序列码检测器，奇偶校验器、CRC（循环冗余）校验器，并附有FPGA的代码和仿真。-The routines including seven order pseudo-random sequence generator, sequence yards detector, parity validator, CRC (cyclic redundancy) validator, and with FPGA code and simulation.
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利用FPGA编程--- -实现“伪随机序列发生器设计”-FPGA programming------- pseudo-random sequence generator design
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基于FPGA伪随机序列产生器，GOLLMANN级联F-FCSR，产生伪随机序列-FPGA-based pseudo-random sequence generator, GOLLMANN cascade F-FCSR, generating pseudo-random sequence
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设计一个简易数字信号传输性能分析仪，实现数字信号传输性能测试；同时，设计三个低通滤波器和一个伪随机信号发生器用来模拟传输信道。(A simple digital signal transmission performance analyzer is designed to test the transmission performance of the digital signal. At the same time, three low-pass filters and a pseudo-ra
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