搜索资源列表
maxshiyan
- 大学vhdl语言实验大全,基于max-plus2平台,内有8-3译码器,8位加法器,数字钟，数码显示，74ls138，8，4位计数器，d，rs触发器，加法器，交通灯等，此原码基于长江大学可编程器件实验箱,如要运行在其他平台上需要重新定义管脚-University VHDL language experiment Daquan, based on the max-plus2 platform within 8-3 decoder, 8 Adder, digital clock, digital d
FEC_EncodeAndDecode
- 实现RS-FEC擦除码的编码与解码，开发环境为VC2003。以解码为例，分析数据报文的API在FecDecInterface.cpp/h中，FEC解码的APIfec.cpp/h中。-RS-erasure code FEC coding and decoding, the development environment for the VC2003. A decoder for example, Analysis of data packets in the API FecDecInterface
RSdecod
- RS 码译码源程序,在Visual c++下可对比4元域上的RS码进行纠错译码.-RS decoder source, in Visual c contrast under four yuan domain of RS error correction code for decoding.
testjiucuo4
- RS纠错解码,xn纠错码原理与方法一书例题目-RS forward error correction decoder, xn principle and method of error-correcting code book cases subject
key_b
- 本程序主要通过外部中断INT0及3.3端口读取PS2键盘值并通过LCD1602显示，键扫描码的解码通过数组方式解码，程序的解码功能主要针对数字及大小写字母和常用标点符号 硬件描述：PS2键盘的时钟线（clk）接89S51的INT0（P3.2）,数据线data接（P3.3） LCD的控制端口分别为： RS = P2^7，RW = P2^6，EP = P2^5，数据端口为P0，液晶显示偏压VL必须接 -This procedure mainly through external int
rs-codec-8-16
- RS[255,223]纠错码verilog源码，包含编码和解码模块，以及testbench等。-Verilog source code for RS[255,223] encoder and decoder, with testbench included.
rscode-1.0
- RS译码器的C源代码,采用了BM算法，钱搜索，和福尼算法求错误值-the rs decoder c code
RSdecoder
- RS信道编码的解码程序。这个适用于解码从信道上接受的编码，从而恢复。-RS decoding channel coding procedures. This applies from the channel decoder to receive the code, thus restoring.
verilogRS
- 该文件为基于fpga的RS（204.188）译码器的verilong源代码，使用的Quartus II的开发环境，已经通过编译，需要者可以自己下载在编译简历工程使用-The document is based on fpga' s RS (204.188) decoder verilong source code, use the Quartus II development environment, has been compiled by the need to download th
reed-solomon_c
- This same code demonstrates the use of the encodier and decoder/error-correction routines. （RS编码和纠错编码的完整程序）-This same code demonstrates the use of the encodier and decoder/error-correction routines. (RS encoding and error correction coding of a c
RS
- RS译码器的设计，使用RS码设计的译码器-RS decoder design, the use of RS code decoder design
RS
- RS译码器的设计源程序--verilog HDL实现-Design of the RS decoder source code-- Verilog HDL
(255_223)-RS-decoder
- 使用VHDL实现（255,233）的RS硬件译码器，详细地介绍了(255，223)RS码硬件译码器的实现流程，并且分析了影响处理速率提高的瓶颈因素，采用RiBM算法实现译码-Use VHDL (255,233) RS hardware decoder, a detailed descr iption of the (255,223) RS code hardware decoder implementation process, and analyze the bottleneck factor
rs_decoder_31_19_6.tar
- RS Decoder RTL verilog Code
rs decoder
- code for Reed solomon decoder..
rs encoder and decoder
- 实现了RS编码的详细的功能，附有程序解释。(Realized the detailed function of RS code, with a program explanation.)