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USB2.0_rtl_ipcore_verilog
- 经过门级网单验证的USB2.0 IP核 RTL代码-net after gate-level verification of USB IP Core RTL code
verificationOfSLMandRTL
- Design for Verification in System-level Models and RTL, very good and classic
OVL
- OVL——基于断言的verilog验证 Verilog数字系统设计:RTL综合、测试平台与验证-OVL- assertion-based verification of Verilog Verilog digital system design: RTL synthesis, test and verification platform
counter
- 详细描述n比特计数器及RTL验证，计数器的位宽用generic语句设置为参数。MY_CNTR是一个n比特二进制的计数器，可以向上向下计数，并可设置计数值，计数器用异步的方式进行低电平复-A detailed descr iption of n-bit counter and RTL verification, the bit counter is set to use generic parameters statement. MY_CNTR is an n-bit binary counter
sdram
- 程序说明: 本次实验控制开发板上面的SDRAM完成读写功能。 先向SDRAM里面写数据，然后再将数据读出来做比较，如果不匹配就通过LED变亮显示出来，如果一致，LED就不亮。 part1是使用Modelsim仿真的工程 part2是在开发斑上面验证的工程 目录说明: part1: part1_32是4m32SDRAM的仿真工程 part1_16是4m16SDRAM的仿真工程 \model文件夹里面是仿真模型 \rtl文件夹里面是源文件 \sim文
ASIC
- 本文介绍了基于标准单元库的深亚微米数字集成电路的自动化设计流程。此流程从 设计的系统行为级描述或 RTL 级描述开始，依次通过系统行为级的功能验证，设计综合，综合后仿真，自动化布局布线，到最后的版图后仿真。在-This article describes the standard cell library based on deep sub-micron digital IC design flow automation. This process from the design of sy
Writing-Testbenches
- 如何写RTL的测试平台，仿真模型，进行系统验证。-Writing Testbenches-Functional Verification of HDL Models(2nd)
Verilog-Digital-System-Design
- Verilog数字系统设计——RTL综合.测试平台与验证 书中的所有源代码-Verilog Digital System Design- RTL synthesis. Test and verification platform for all the source code for the book
switch
- It is switch design (RTL) implemented in verilog and have a verification environment in verilog
VerilogDesignand-test_PdfPCode
- Verilog 设计与验证源码+PDF，经典教程，对与RTL和状态机的理解有很大帮助，适合FPGA开发工程师。-Verilog design and verification source+ PDF, classic tutorial, and state machine understanding of RTL helps a lot, suitable for the FPGA development engineers.
coding_and_synthesis_with_verilog
- In the semiconductor and electronic design industry, Verilog is a hardware descr iption language (HDL) used to model electronic systems. Verilog HDL, not to be confused with VHDL (a competing language), is most commonly used in the design, verificati
verification-of-SLM-and-RTL
- VERIFICATION OF SLM AND RTL
verilog
- verilog数字系统设计-rtl综合测试平台与验证 书中源码-verilog Digital System Design-rtl test platform verification book source
formal_verification
- 现在最流行的RTL设计方法之一，本书为全球流行的设计入门书籍(One of the most popular RTL design methods nowadays, this book is an introductory book for popular design all over the world.)