搜索资源列表
dds.rar
- 这是用ALTERA里的DSP BUILDER里做的DDS模块，可以在EP1C20400里下载并通过SIGNAL TAP进行在线测试。,It is used inside the DSP BUILDER where ALTERA do DDS module, you can download a EP1C20400 through SIGNAL TAP-line testing.
TM320C54x(v2a.asm)
- ECE345, Visual-to-Audio Electronic Travel Aid Code for TM320C54x (v2a.asm) download This project involves the design and implementation of a audio synthesis device that converts moving images into audio signals. The system is built on a TM320C5
zishiyingxindaojunhengqi
- 使用下面的参数设计信道均衡器，其中使用两个独立的随机数发生器，一个用x(n)来表示，用来测试信道；另一个用v(n)来表示，用来模拟接收器中的加性白噪声的影响。序列x(n)是x(n)=±1的伯努利序列，随机变量x(n)具有零均值和单位方差。第二个序列v(n)具有零均值，其方差由信噪比决定。均衡器有11个抽头。-Use the following parameter design of channel equalizer, which uses two separate random number
fjq5
- 视频信息的复接是把两个或两个以上支路信号依据时分复用的方式合成一路信号, 在接收端则由数 字分接器把合路信号分接为原来的支路信号.-Multiplexing video information is to slip two or more signals based on the way synthesis of the way time-division multiplexing signal, at the receiving end by the number of splitters
tut_signaltapII_verilogDE2
- Altera公司原版设计手册，关于signaltap ii。-This tutorial explains how to use the SignalTap II feature within Altera’s Quartus R II software. The Signal- Tap II Embedded Logic Analyzer is a system-level debugging tool that captures and displays signals in
thesis-blind_equalization
- 自适应均衡器设计用于抑制信号失真，自适应均衡器节拍系数是时变调整的。-Adaptive equalizers remove signal distortion attributed to intersymbol interference in band-limited channels. The tap coefficients of adaptive equalizers are time-varying and can be adapted using several methods
LinPF
- This a VHDL module that implements linear prediction filter based on NLMS (normalized least mean square). The module takes complex signal as input and output comlex signal (real and imaginary). Tap size is 4, bit precision is set to 12 bits.-This i
lms_rsl
- 利用lms算法和rls算法，对通过给定系统h的随机信号进行自适应滤波，通过抽头w对系统进行逆辨识与辨识，同时产生MSE 即均方误差，来描述对信号恢复的效果。-Using lms algorithm and rls algorithms h through a given system adaptive filtering of random signals, the system through the tap w reverse identification and recognition,
signaltapII_verilogDE2
- This tutorial explains how to use the SignalTap II feature within Altera’s Quartus R II software. The Signal- Tap II Embedded Logic Analyzer is a system-level debugging tool that captures and displays signals in circuits designed for implement
bujinmada
- 步进马达的正反转问题，与节拍控制。根据单片机引脚输出波形信号，实现-Reversible stepping motor problems, and tap control. According to the microcontroller pin output waveform signal,
d4ef13.ZIP
- 基于振动信号的变压器分接开关触头故障诊断Based on the vibration signal of the transformer tap switch contact fault diagnosis-Based on the vibration signal of the transformer tap switch contact fault diagnosis
junhengqi
- 3抽头迫零均衡器，5抽头迫零均衡器，以及恢复信号波形-3-tap zero forcing equalizer, the 5-tap zero forcing equalizer, and the restoration of the signal waveform
sub-band-coding
- 子带编码是一种以信号频谱为依据的波形编码方法，首先用一组带通滤波器将输入信号按频谱分开，然后让每路子信号通过各自的自适应PCM编码器（ADPCM）编码，经过分接和解码再复合成原始信号。-In sub-band coding is a waveform signal based on the spectrum coding method using a first set of band pass filters to separate an input signal spectrum, and
signal_tap_ii_test
- Quartusii环境下利用signal tap ii工具进行仿真的实例，很好的参考实例-Under Quartusii environment using signal tap ii tools for simulation examples, a good reference example
uhd-master
- This paper investigates the Wiener and least mean square (LMS) algorithms in the design of traversal tap delay line filters for the purpose of compensating the effect of the communication channel. The designed equalizers remove the distortion
SignalTap-II-instruction
- 对于学习FPGA的同学来说仿真是必不可少的流程 但是仿真的方法signal tap是必须掌握的-For students learning FPGA simulation is an essential process but the simulation method tap signal is a must
CA_Code
- 本源码是对类GPS信号中的C/A码的仿真，通过改变移位寄存器的选择抽头，可实现不同C/A码的产生。-The source is the class GPS signal in C/A code simulation by changing the shift register tap selection can be realized to generate different C/A code.
fft_analyze
- 利用Altera的IP核，实现FFT算法使用信息流模式读写，使用SignalTap II嵌入式逻辑分析仪观察信号，A/D只要是并行的8位芯片都可以。-Achiving FFT by using Altera IP Core,you can observe the signal by the embedded logic analyzer Signal Tap II,as for A/D device, it s suitable for a parllarel 8 bits A/D device
SignalTapII学习笔记
- signal tap ii FPGA开发测试模块 Verilog HDL 语言(signal tap ii testmodule Verilog HDL language)