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generic_avalon_sram
- 一个比较有参考价值的sram IP核，对SOPC感兴趣的人士有一定的指导意义！该程序是采用avalon总线，可以直接内嵌进SOPC Builder。
altera_avalon_cy7c1380_ssram
- 关于altera的SRAM的读写控制IP代码，有兴趣的朋友可以下去
SRAMCotroller
- 一个SRAM控制器的IP核，很不错，有兴趣的朋友可以下去
SRAM_16Bit_512K
- Verilog 编写的IP核，512K的16位SRAM
SRAM_16Bit_512K_0
- SRAM的ip核，niosii，avalon总线的-SRAM' s ip nuclear, niosii, avalon bus
altera_up_avalon_sram
- 基于Avalon的SDRAM控制器IP核-Avalon SRAM Controller
DE2_NIOS_LITE_SRAM
- DE2-SRAM-IP-CORE 需要开发ip core的朋友可以参考哦 ~-DE2-SRAM-IP-CORE need to develop friends can ip core reference Oh ~
Protecting_FPGA
- How to protect your FPGA design (IP) on SRAM based FPGA s against copying.
SRAM_Controller
- Altera University Program的Avalon总线IP核，SRAM控制代码，可以解压后直接挂载在Avalon总线上 -Altera University Program of the Avalon bus IP core, SRAM control code can be directly mounted after decompression in the Avalon bus
SRAM_Controller
- altera 大学计划 程序包的sram controller ip-altera University Program package sram controller ip
ALTERA_SRAM_IP
- ALTERA公司的SRAM IP核，加快设计流程-ALTERA company SRAM IP cores, speeding up the design process
mb_support_sram
- 配置MB软核使其支持，SRAM并在此基础上做UART测试，文章（我写的呵呵）详细的讲了如何从最对SRAM时序进行配置，如何设置相应参数，如何生成硬件平台，实在是入门必备。-configure the MB ip core to support SRAM .and ,do a test with dsp uart
SRAM
- 使用Verilog语言编写的SRAM读写程序,不用添加IP核,在Xilinx Spartan-6上运行通过,是很好的Verlog程序-SRAM using Verilog language literacy program, do not add the IP core in Xilinx Spartan-6 run through, is a very good program Verlog
HT6X1X_FAQV1.8
- HT5X1X FAQ 钜泉 HT5X1X FAQ V1.1 钜泉光电科技(上海)股份有限公司 Tel...6 1.8 RTC 时间修改(HT602X series MCU is designed for the new generation of smart meter applications in the country. The kernel uses a ARM Cortex-M0 processor which was highly optimized in size, power c
HEX2MIF
- QUARTUS II SRAM/ROM初始化需要的HEX文件与Keil产生的HEX格式不同；该Modelsim程序，将Keil产生的Hex转换成，Quartus可以是识别的MIF格式；(The QUARTUS II SRAM/ROM initialization needs HEX files which are different from those generated by Keil. The Modelsim program converts Hex generated by Keil
sram ip verilog
- tsmc 0.18um ip model