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vedio_collection.rar
- 在这个压缩包里，包含了关于视频采集知识的一些基本的介绍。并且在里面还包含了一个基于spartan-3E的视频采集实验,The compressed pack contains some fundemental introdutions about video collections .What s more ,there is a referenced lab on vedio collection which is based on spartan-3E!
ISE_lab19
- 俄罗斯方块VHDL实现，。该设计由下面模块组成：键盘输入模块，游戏控制模块，图像显示模块，文字显示模块，存储单元，复用单元和VGA 控制模块组成。其中图像显示模块和文字显示模块复用VGA 控制模块。游戏控制模块，图像显示模块和文字显示模块通过存储单元交换数据。-Tetris VHDL implementation. The design consists of the following modules: Keyboard input module, the game control modul
CPU
- 一个多周期CPU的完整设计，quartus平台，Verilog实现，内含实验报告，和详细的各模块功能表-Complete a multi-cycle CPU design, quartus platform, Verilog implementation, includes lab reports, and a detailed menu of each module
MultipleNumbersCalculator
- Multiple Numbers Calculator (source code and LAB notes)
matladfilefordecom
- mat lab codes for watermarking
pingpang
- 本实验在实验室实现了对于简易的乒乓球游戏的模拟，以发光二极管的移动来模拟乒乓球的移动，转向表示击球，并实现积分。-In this study, achieved in the lab for a simple table tennis game simulation, in order to light-emitting diodes to simulate the movement of table tennis movement, turning that ball and achieve
WatchForLab
- This was the first lab assigmnet in the course CPU Architecture, creat a basic watch
experiment5_1
- VHDL实验5，七段数码显示译码器设计。1）用VHDL设计7段数码管显示译码电路，并在VHDL描述的测试平台下对译码器进行功能仿真，给出仿真的波形。-VHDL Lab 5, Seven-Segment Display Decoder. 1) design using VHDL 7 segment LED display decoder circuit, and the VHDL descr iption of the decoder under test platform for functio
VideoLoopback
- VHDL写的完整的图像采集与处理的程序，经实验，完全调通 -vhdl program about the picture process,and it is doing well in the lab.
VERILOG_VLSI_LAB_MANUAL
- VHDL Lab Manual useful for lab purpose
lab
- VHDL Lab manual useful for experiment purpose
50973937-VHDL-Report
- Introduction This report is organized as following.First, it is divided into chapter 2 to chapter 12. Within each chapter, VHDL code is presented at the beginning of each problem. Then, simulation results for these codes is also included. For s
vhdl1
- vhdl lab for using labarories
lab3
- VHDL Lab 3 – Arithmetic & State Machines In this lab we will look at arithmetic circuits that add, subtract, and multiply numbers. Each type of circuit will be implemented in two ways: first by writing VHDL code that describes the require
A-Simplified-VHDL-UART
- In embedded systems, the processor that we choose for our design may not come with built-in peripherals. Therefore, designers will have to implement these devices in hardware keeping in mind that they will need to interface to the processor. In this
VHDL-Design-lab-presentation
- Presentation introduction to VHDL language and some useful experiments
DESIGNS-WITH-VHDL
- Lab sheet for VHDL language contain six different experiments 1 introduction to vhdl 2 data flow modelling 3 sequential modelling 4 structural modelling
m.e-lab
- vhdl verilog code for alu operation pll,biy sliced processor
vhdl-lab-report
- vhdl实验报告，关于4位选择器，在maxplusII下运行-vhdl lab report
LAB
- SAM VHDL编码，包括数据选择器，加法器，简易逻辑电路，有限状态机等(FSM SAM ALU and many other different parts)