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Simulator
- C实现模拟与或非门的逻辑电路,可以多元件输入,支持元件延时,可以绘制输出波形-C simulation and implementation of logic circuits or door, you can enter many components to support the delay components, you can draw the output waveform
shiziluoji
- 三位二进制加1与加2计数器 :三位二进制模5计数器。当外部输入X = 1时,计数器加2计数;外部输入X = 0时,计数器加1计数。“模5”为逢“5”进1计数。 原始条件:使用D触发器( 74 LS 74 )、“与”门 ( 74 LS 08 )、“或”门( 74 LS 32 )、非门 ( 74 LS 04 ),设计三位二进制模5计数器。 -The three binary counter plus 1 and plus 2 : three binary mod 5 counter. X =
verilog_stand_cell_lib
- verilog 门级设计及仿真标准单元库,包含142个基本的逻辑门单元。可用于VERILOG开发实现与或非、加法、减法、累加等基本的逻辑运算单元,实现精确的逻辑仿真。-verilog gate-level design and simulation of a standard cell library contains 142 basic logic gate unit. VERILOG implementation and can be used to develop or, addition