搜索资源列表
multiper
- 用xilinx写的vhdl乘法器。是二进制的两位乘法器。里面含有代码和电路图。-Written in VHDL using Xilinx multiplier. Binary multiplier is two. Which contains code and circuit diagrams.
hierarch_unit.tar
- 该代码是布斯乘法器代码，用于了解布斯算法，本人也是初学者。-err
multi
- 8位乘法器，Quters编译环境VHDL代码-pluter VHDL Quters
ff_mul
- 源码伟 伽勒华域乘法器的verilog代码，经过验证-Source-wei Galle Chinese domain multiplier verilog code, a proven
multiM_N_M
- 三十二位乘法器，功能简单易懂，好理解，可综合代码-Thirty multiplier functions easy to understand, easy to understand, the code can be integrated
mux16
- 一个流水线的16X16的乘法器，经过验证，很好的代码-16X16 multiplier, a pipeline proven good code
streamline_div
- 一个资源很省的乘法器,代码为Verilog代码,8位除法器，除法结果在8个时钟后输出.代码也可自行扩展到更大位宽.-A resource is the province of the multiplier, code for Verilog code, 8-bit divider, division results in eight clock output. Code can also extend themselves to greater width.
ParallelSerialMult
- 用verilog代码来实现并行序列乘法器，采用乘法器结构，读者可以自行编译，-Use verilog code to implement a parallel sequence multiplier, using the multiplier structure, readers can compile their own,
第一次实验booth乘法
- mars上运行的booth乘法器，包括报告以及代码(Booth multiplier running on Mars)