搜索资源列表
bit_synch
- 本人写的MSK解调位同步完整程序，基于QuartusII90环境，采用verilog语言编写，程序简练，可靠性高，而且暂用资源少，适合CPLD器件。文件包含仿真和说明，欢迎下载！-I write a complete program MSK demodulation bit synchronization, based on QuartusII90 environment, using verilog language, procedures, concise, high reliability
wei
- 位同步的verilog实现，利用窄脉冲来延迟或提前相位达到同步-Verilog achieve bit synchronization using narrow pulses reach synchronization to delay or advance phase
Freq_counter_ise12migration
- 用verilog实现的一个频率计数器，可分别在不同的频率下计数（自己设定），里面有几个有用的小模块，分频，计数，显示，同步，进位等-Verilog to achieve a frequency counter, respectively, in different frequency count (set), there are several useful modules, divide, count, display, synchronization, binary, etc.
counter
- verilog 写的一个增减计数器的例子，可用于位同步时钟提取中，已经经过验证，可直接添加到自己的工程中。-Verilog write an increase or decrease the counter example, can be used to extract a synchronous clock, has been validated and can be directly added to your project.
wei
- 实现位同步提取的代码部分，使用Verilog语言编程。(Implementing the code part of the bit synchronization extraction)
同步
- 基于FPGA的位同步算法的verilog实现(Verilog implementation of synchronization algorithm)