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multi8x8
- 该源码为8位乘法器的VHDL语言描述，由一个8位右移寄存器，2个4位加法器例化成8位加法器，一个16位数据锁存器构成。采用移位相加的方式，从被乘数的低位开始，与乘数的每个位移位相加求和。最后实现其乘法器功能。-The source code for the 8-bit multiplier in VHDL language to describe, from an 8-bit right shift register, two 4-bit adder example into 8-bit add
BCD_adder_4digit
- 首先将最大四位的整数转换成BCD码，然后用VHDL设计一个4位BCD码加法器，-BCD_adder_4digit
component32adder
- 首先设计简单的4位二进制加法器，然后利用例化语句级联成为32位二进制加法器-First of all, the design of a simple binary adder 4, and then the use of statements were to become 32-bit binary cascade adder
4-ahead_Adder
- 用Verilog HDL语言实现超前进位加法器的逻辑功能,通过ModelSim软件对4位超前进位加法器设计的仿真.-With the Verilog HDL language-ahead adder logic functions, by ModelSim software 4-ahead adder design simulation.
adder
- 实现各种加法器的功能，包括4位及8位超前进位，4位及8位逐次进位加法-The various adder functions, including four and eight lookahead, 4-bit and 8-bit successive-carry adder