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M_design
- 设计一个简单的8比特ALU和一个简单的存储器，是用VerilogHDL实现的，这是个题目及其解析-Design of a simple 8-bit ALU and a simple memory, is used VerilogHDL realized, this is a subject and its analytic
ALU_design
- 设计一个简单的8比特ALU的源代码，是用VerilogHDL实现的-Design of a simple 8-bit ALU s source code is achieved using VerilogHDL
ALU
- ALU加法器的设计，实现带进位的加法运算！-ALU adder design, the realization of the adder into the bit computing!
ALU-FP
- ALU floating point 8 bit
cpu16
- 实现一个16位CPU。该CPU使用精减指令集，是一个五段流水线的结构。包括取指令(IF)、读寄存器(RD)、运算器(ALU)、内存读写(MEM)和写回(WB)。-The realization of a 16-bit CPU. Streamline the use of the CPU instruction set is a structure of five lines. Including fetch (IF), register read (RD), arithmetic logic u
ALU_32
- 32 bit ALU design,LU Operations: This input specifies the ALU operation to be used during the acquisition process. The ALU operations are divided into logical operations and two classes of arithmetic operations. The two classes of arithmetic operatio
Alu-4bit
- alu 4 bit with verilog in modelsim and work correct
8-alu
- 8-bit alu design...it has arithematic and shift operation-8-bit alu design...it has arithematic and shift operation....
ALU
- Arithmetic logic unit, add, subtract,bit shifter
32Bitaludesign
- Design of simple 32 bit alu for SPARTAN 3 paltform
Alu
- 4位ALU逻辑运算器，用VHDL语言编写-4-bit ALU process using VHDL
new_yasodai_code
- ile Format: PDF/Adobe Acrobat - Quick View by SS Basha - 1963 - Related articles HIGH SPEED MULTIPLIER FOR ALU S USING MINIMAL ... VHDL codes for 8x8-bit signed numbers and successfully simulated and .... a partial product is generated from the m
Jammuna_code
- ile Format: PDF/Adobe Acrobat - Quick View by SS Basha - 1963 - Related articles HIGH SPEED MULTIPLIER FOR ALU S USING MINIMAL ... VHDL codes for 8x8-bit signed numbers and successfully simulated and .... a partial product is generated from the m
4BitALU
- This 4-Bit ALU performs four below operations: 00 (S14=0 & S04=0) : OR 01 (S14=0 & S04=1) : AND 10 (S14=1 & S04=0) : ADD 11 (S14=1 & S04=1) : SUB
alu_Acc_16bit
- Alu 16 bit VHDG Altera project
8bit-ALU
- 8位alu logisim实现 可加减或-8 bit alu， logisim bulit
vhdsl_4bit_alu
- a 4 BIT alu implemented using vhdl as core language. Works fine on spartan 3e. tested and verified
ALU-master
- alu 4 bit, add, sub, com(Perform basic operations, addition, subtraction, comparison)