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VHDLgdewrrrrrrrrrrrr
- 本设计中选用目前应用较广泛的VHDL硬件电路描述语言，实现对路口交通灯系统的控制器的硬件电路描述，通过编译、仿真，并下载到CPLD器件上进行编程制作，实现交通灯系统的控制过程。EDA技术是用于电子产品设计中比较先进的技术，可以代替设计者完成电子系统设计中的大部分工作，而且可以直接从程序中修改错误及系统功能而不需要硬件电路的支持，既缩短了研发周期，又大大节约了成本，受到了电子工程师的青睐。实现路口交通灯系统的控制方法很多，可以用标准逻辑器件、可编程序控制器PLC、单片机等方案来实现。但是这些控制方
trafficontrol
- 使用verilog编写的交通灯控制程序，各方向通行时间可调，绿灯5s闪烁，在maxplus下调试通过，附仿真波形，在EP系列实验板上测试成功-use Verilog prepared by the traffic lights control procedures, the passage of time adjustable direction, green 5s flickered in maxplus under debugging, simulation waveforms with t
cpu-maxplus
- MaxplusII编写的简易cpu，可实现简单加减法等操作-MaxplusII summary prepared by the cpu can realize simple addition and subtraction, etc
vhdl
- 基于MAXPLUS II 的软件设计，这里面有几个小程序，用于VHDL的GDF设计，含有LED数码管的显示驱动程序，还有3选一，十选一程序。-II FPGA-based design software, there are several small procedures, GDF for VHDL design with a digital LED display driver of the procedures, there is a three elections. 10 election
VHDlhdb3
- VHDL _HDB3编译码,基于MAXPLUS平台,有完整的仿真波形.
thelabreportofthePrinciplesofComputerComposition.r
- 计算机组成原理实验报告：包括运算器组成实验，存储器，微控制器等实验-Principles of Computer Organization Experimental report: composition of the experimental devices, including computing, memory, microcontroller and other experimental
MAXPLUS2_sch_design
- maxplus II 原理图设计使用教程。-maxplus II schematic design tutorials.
2psk_final
- 2dpsk,maxplus软件,包含连接原理图\各个模块程序代码,可运行,管脚已经封装,可直接下载到FPGA芯片-2dpsk, maxplus software, including schematic connection \ each module code can be run has been pin package, can be directly downloaded to FPGA chip
MAXPlus_license11.0
- use for max+plus11.0,含license.dat-for max+plus11.0 ,include license.dat
miaobiao
- 计时器的最长计时时间为l小时, 为此需要一个6位的显示器, 显示的最长时间为 59分59.99秒。具有开始暂停功能的秒表-miaobiao
modle
- 计算机组成之模型机实验,有在maxplus上的源文件和课程设计报告-Composed of a computer model of machine experiments, there is the maxplus source files and programs on the design report
3FSK.vhd
- 利用MAXPLUS作为仿真工具，用VHDL语言编程，采用频率键控法实现3FSK调制。对输入的系统时钟分别进行2分频，4分频和8分频得到这3种频率。通过对数字基带信号进行双二进制编码得到3个电平值，把它们作为三选一开关，来分别选择不同的频率值、选择不同的信号，从而实现3FSK调制。-As a simulation tool used MAXPLUS using VHDL language programming, using frequency shift keying modulation me
poc
- The purpose of this project is to design and simulate a parallel output controller (POC) which acts an interface between system bus and printer. The Altera’s Maxplus II EDA tool is recommended and provided for simulation.-A parallel output con
counter
- maxplus 设计的 10位计数器-maxplus 10-bit counter
8eda
- 八位抢答器，在ＭＡＸＰＬＵＳ平台下动行。用VHDL编的八位抢答器，EDA课设的一个经典题目源程序-8 Responder, in MAXPLUS platform moving line. With a series of eight Responder VHDL, EDA courses located the source of a classical subject
Maxplus-timing-simulation
- 主要介绍Max_plus_的时序仿真与时序分析，对刚入门的很有帮助意义。-Introduced Max_plus_ timing simulation and timing analysis, meaning just getting started helpful.