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PLL_PLV
- 锁相回路可视为一个输出相位和输入相位的回授系统用以同步输入参考讯号和回授后输出信号。并让其操作同样的频率。如(图一)所示，简单锁相回路[3,4]是由三个电路构成，分别为相位侦测器（Phase Detector）、回路滤波器（Loop Filter）、压控荡器（VCO）-phase-locked loop can be regarded as a phase output and input phase feedback system for synchronous reference input
发射部分采用锁相环式频率合成器技术
- 发射部分采用锁相环式频率合成器技术， MC145152和MC12022芯片组成锁相环，将载波频率精确锁定在35MHz，输出载波的稳定度达到4×10-5，准确度达到3×10-5，由变容二极管V149和集成压控振荡器芯片MC1648实现对载波的调频调制；末级功放选用三极管2SC1970，使其工作在丙类放大状态，提高了放大器的效率，输出功率达到设计要求。,Part of the launch phase-locked loop frequency synthesizer using technolog
pllzijida 自己利用PSCAD搭建的２种PPL锁相环
- 自己利用PSCAD搭建的２种PPL锁相环，能够自己调节ＰＩ参数，并与自带的ＰＬＬ进行了测试比较。-PSCAD build their own use two kinds of PPL phase-locked loop to adjust the PI parameters of their own, and with the built-in PLL more
altclklock0
- 用fpga进行串行通信，内部附用锁相环进行控制传送和接受-Fpga using serial communication with the internal phase-locked loop with send and receiving control
costas_loop
- 使用改进的COSTAS环实现锁相环（PLL），应用于高动态的数字化接收系统-COSTAS Central improved to achieve phase-locked loop (PLL), used in high dynamic digital reception system
PPL
- 该论文设计了一个基于锁相环技术的倍频器，用Proteus软件仿真，效果不错。-Phase-Locked Loop
suoxiang
- 该文件运用matlab仿真工具仿真通信中的关键技术之一，锁相环。采用不同的调制方式。-The document the use of simulation tools for communication matlab simulation of one of the key technologies, phase-locked loop. Different modulation.
PLL
- Programs for the book of Phase Locked Loop :design simulation and applications-Programs for the design of Phase Locked Loop circuits
estimatingandintepretatininstantaneousfrequency.ra
- 瞬时频率的解释和瞬时频率估计算法的介绍，回顾目前存在的一些瞬时频率估计算法以及作者提出的新的算法-This paper, which addresses the important issue of estimating the instantaneous frequency (IF) of a signal, is a sequel to the paper which appears in this issue, and dealt with the concepts relat
pll
- 摘要:叙述了全数字锁相环的工作原理,提出了应用VHDL 技术设计全数字锁相环的方法,并用复杂可编程逻辑器件CPLD 予以实现,给出了系统主要模块的设计过程和仿真结果。-Abstract: This paper describes the working principle of an all-digital phase-locked loop is proposed application VHDL technical design an all-digital phase-locked loo
PLL
- phase locked loop simulation
pll
- Phase locked loop (PLL) design pricniples
PracticalPhaseLockedLoopDesign
- Practical Phase-Locked Loop Design
weitongbu
- 用数字锁相环实现位同步信号提取，包含各个模块的电路设计程序。-To achieve bit synchronization with digital phase-locked loop signal extraction, each module contains the circuit design process.
pll
- 锁相环的常见问题解答，对于全面理解，和研究锁相环的各种指标，有非常好的指导作用-PLL FAQ for a comprehensive understanding of, and the various indicators of phase-locked loop, a very good guide
BLOCK-PHASE-DEMODULATOR
- 块相位估计－Block Phase Estimation(BPE)取代了传统的锁相环(PLL)结构，以取模 (Modulo)运算为基础，而且使用创新的平均器，既简化了算法结构，又大大方便于硬件实现，同时为芯片设计提出了新的思路；但国内研究较少，资料极其匮乏；文章在对BPE的原理与结构进行较为深入的介绍与分析的基础上，对BPE进行了由浅入深的仿真，解决了部分跟踪器－SECTOR TRACKER(ST)的问题，给出了部分仿真结果；最后，分析了BPE的优缺点，给出了改进的方法。-Block Phase
Matlab-Kalman
- In statistics, the Kalman filter is a mathematical method named after Rudolf E. Kalman. Its purpose is to use measurements that are observed over time that contain noise (random variations) and other inaccuracies, and produce values that tend to be c
Loop-filter-MB1504
- 环路滤波器参数设计软件，有效支撑锁相环系统-Loop filter parameters design software，Effectively support the phase-locked loop system
Phase-locked-loop
- 用于解决单相并网中的锁相环问题，并实现相应的仿真验证探究。-To solve the problem of single phase grid connected in phase locked loop
All-Digital-Phase-Locked-Loop-Design-and-Implemen
- All Digital Phase Locked Loop Design and Implementation