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38.58
- 基于VDHL的38译码器的实现与58分频器的实现 FPGA主芯片：CycloneII EP2C35F672C6-Based on VDHL decoder 38 with the divider 58 to achieve the main FPGA chip: CycloneII EP2C35F672C6
keshe_qd6
- 用VDHL硬件描述语言实现六路抢答模块，满足互锁功能，即同时按下只有一个输出。-Using VDHL hardware descr iption language to realize six road module, meet the interlocking functions, namely, while pressing the only one output.
Lab
- 硬件编程实现处理器。包括ALU、编译器、单周期处理器、流水线处理器等多个部分。-Processor by VDHL
traffic light controller
- Traffic Light Controller VDHL code