搜索资源列表
sdr_sdram_control
- 一个SDRAM控制器，verilog语言设计，并在ISE上仿真实现。（内部包含多个verilog程序）-sdram-controller,use verilog langguage,it s run sucessfull
Xilinx_ISE_11.1_licgen_v3
- xilinx_ise 11.1 破解，这个版本支持V5的器件，V2一下不支持-Xilinx_ISE_11.1_licgen
ISE
- XINILX最新开发软件版本,ISE11.1,这里的资源最好,比讯雷快得多 -XINILX latest development software version, ISE11.1, where the resources of the best, much faster than the Thunder
AM_VHDL
- AM Demodulator using VHDL for Xilinx FPGA. ISE software
eetop[1].cn_ise_book
- Xilinx ISE 9.x fpga&cpld设计指南 光盘附带内容
xilinxisev6.1ikeygenror
- xilinx ise 6.1 keygen
fir_compiler_ds534
- 详细的描述了XILINX ISE软件里的IP核的内部结构。详细的介绍了滤波器的各个内部机构和各个功能。-A detailed descr iption of the internal structure of the the XILINX ISE software IP core. Detailed introduction of various internal organs and the various functions of the filter.
LED_TEST
- Verilog的LED闪烁程序，xilinx ISE开发环境-Verilog LED flashes, Xilinx ISE development environment
irig_b
- 用来实现IRIG_B码的解码程序，在XILINX ISE上运行过没有问题，-Used to achieve IRIG_B code decoding process, in XILINX ISE run-off is no problem,
xilinx_ise
- Xilinx ISE 14.4 Lincense，实测可用-Xilinx ISE 14.4 Lincense, actual available
yimaqi_beh
- 8位计数器作业中的behavioral描写，没有带testbench，已经通过-1. Construct VHDL models for 74-139 dual 2-to-4-line decoders using three descr iption types, i.e., behavioral, dataflow and structural descr iptions. Synthesize and simulate these models respectively in the en
ExamTechAss2009
- un controller pi par le langage VHDL xilinx ise design 13.2
Greedy_snake
- 利用Xilinx ISE平台在FPGA实验板和VGA显示屏上完成简单的贪吃蛇游戏-Use Xilinx ISE platform to complete a simple Snake game on FPGA experimental board and VGA display
Washing_VHDL-v1
- 一个全自动洗衣机，三个状态及显示。 开发环境为xilinx ise-a autowasher with 3 states
uart2
- 基于Xilinx ISE的uart传输代码，使用verilog语言完成-Based on Xilinx ISE uart transmission code, completed with verilog language.
3-example_dt_2
- Vhdl编写的数码管驱动，动态7段码，FPGA实验板，Xilinx ISE实验环境-Vhdl write digital tube drive, dynamic 7-segment code, FPGA experimental board, Xilinx ISE experimental environment
Counter3
- 基于Xilinx 的ISE 14.7 的计数器程序，包含testbench文件和约束文件-Based on the Xilinx ISE 14.7 Counter program, including testbench and constraints files
clk_div3
- 基于XIlinx ISE，用Verilog语言实现3分频电路，适合初学者-Based XIlinx ISE, Verilog language using the frequency dividing circuit 3, suitable for beginners
enhancement
- 基于Xilinx ise软件平台的codelock的编程与实现，简单功能(Programming and implementation of codelock based on Xilinx ISE software platform, simple function)
Design
- 利用Xilinx ISE用Verilog编写的计算器(Using Xilinx ISEalculator and register heap program written in Verilog HDL language)