搜索资源列表
multipilier8x8_spice
- 用spice描述的8x8改进Booth码加wallance压缩的乘法器，并且进行了优化，时间性能相当高-the improved Booth coding plus wallance multipliler ,I have optimized it which gained short time and performance,it is descr ipted by spice
adder17
- 实现17位加法，利用一个16位超前进位加法器和一个一位全加器构成的一个有进位输入和进位输出的17加法器，并且16位加法器利用的使四位超前进位加法器构成。它在booth乘法器设计中经常用到。可以使初学者对模块的调用了解更加透彻。-Adder 17 to achieve the use of a 16-bit CLA, and a one-bit full adder composed of a binary input and binary output of the adder 17, and
booth_mul
- booth乘法器，通过booth编码相乘，包括了testbench-booth multiplier, multiplied by booth encoding, including the testbench
multiplier-
- 模拟计算机中乘法器的运行过程，用到了Booth算法-The operation of the computer simulation of the multiplier process, use of the Booth algorithm
booth_multiplie_module
- 利用verilog实现的Booth算法乘法器，对想学习乘法器的将会有很大的帮助.-Booth algorithm verilog realization use multipliers, the multiplier will want to learn a great help.
4booth_multiplie_module_2
- 采用Verilog对Booth算法乘法器的改进，对想学习乘法器的会有很大的帮助。-Improved algorithm using Verilog Booth multiplier, multiplier want to learn to have a lot of help.
Booth2_final
- 该文件是booth乘法器的verilog源代码，经过最终的仿真，可以直接运行-This file is booth multiplier verilog code, after the final simulation, can be directly run
第一次实验booth乘法
- mars上运行的booth乘法器，包括报告以及代码(Booth multiplier running on Mars)
modified_booth_multiplier
- quartus ii项目文件包，功能是改进的booth乘法器，节省时钟，已完成仿真。(This zip file contains a quartus ii project, which can fufill multiple function. It is done by using a modified booth multiplier.)