2倍抽取14位的3级CIC滤波器的FPGA实现的verilog代码-cic filter

用verilog语言实现一个3级、抽取率为2的8位hogenauer CIC抽取滤波器-Verilog language to achieve a 3, the extraction rate of 8 hogenauer CIC decimation filter

CIC Filter 实现的matlab源码.里面使用MATLAB，verilog，c++混合实现CIC抽取滤波器-CIC Filter achieve matlab source. Inside using MATLAB, verilog, c++ hybrid implementation CIC decimation filter