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interleaver
- This is a convolutional interleaver code written in verilog, the ram is sram with ram_ncs, ram_nwe, ram_noe characters.
conv_vhdl
- 用Verilog实现卷积码（2，1，2）的编码器，采用状态机来完成在modelsim下的仿真-Verilog implementation using convolution code (2,1,2) encoder, using a state machine to complete the modelsim simulation under the
k_9_rate_1-2_VHDL
- viterbi generator its very good for convolution
prepha_conj
- 本代码用VHDL实现了复数的卷积，也许对你会有用-this code written by VHDL completes the convolution of complex numbers,which may be quite helpful to you.
viterbi_1
- low power convolution encoder and Viterbi decoder using vhdl code