搜索资源列表
verilog
- 基于QUATEUS2的设计一个8位频率计verilog语言编程-The design is based QUATEUS2 an 8-bit frequency counter verilog programming language
frequencycounter
- 一个简单大家容易看的懂的频率计设计程序，可以实现自动换挡功能。-A simple and easy to see to understand all of the frequency counter design program that can automatically shift feature.
verilog
- 包含了许多verilog编程的实用例子，且有运行之后的V文件，很完整-verilog
LIP1701CORE_system_watchdog
- System watchdog verilog code
counter
- there is a text file of code for 8 bit up counter in verilog.
Verilog_0-9999_counter
- 用Verilog语言实现的0-9999计数器-0-9999 counter Verilog language
counter8
- 基于verilog的8位计数器的编写，有测试程序，并且测试通过-Based on the 8-bit counter verilog preparation, test procedures, and test by
The-decimal-counter
- 用verilog实现的十进制计数器(异步复位)-The decimal counters (asynchronous reset)
counter
- 采用VERIlOG HDL语言设计的一个加法器项目，简单可靠，并把其中测试平台程序加入其中-VERIlOG HDL language designed using an adder project, simple, reliable, and to join the program in which the test platform
Counter
- verilog source code of programable counter
counter
- verilog 写的一个增减计数器的例子，可用于位同步时钟提取中，已经经过验证，可直接添加到自己的工程中。-Verilog write an increase or decrease the counter example, can be used to extract a synchronous clock, has been validated and can be directly added to your project.
counter
- 基础的计数器。4位。Verilog HDL-Basic Counter. Four bit.Verilog HDL
zonghe
- 这是一个verilog编写的计数器，基于quartusii软件，自动计数并显示在数码管上-This is a counter verilog prepared based quartusii software automatically counted and displayed on a digital
second-and--minite-and-hour-counter
- 利用Verilog语言实现时分秒计时功能，并用modelsim仿真出波形。-implementate when minutes timing function using Verilog language, and simulating waveform in the modelsim
counter
- Counter using Verilog
FreqCounter_1_12
- verilog code on frequency counter
cnt12
- 十二进制计数器，基于verilog HDL实现。(Twelve decimal counter)
gray_counter
- 格雷码计数器实质包含了三个部分 格雷码转二进制、加法器、二进制转格雷码。通过quartus II 自带的Modlesim仿真验证了 能够实现二进制和格雷码之间的转换(Gray counter essence contains three parts, gray code to binary adder, binary gray code conversion. Modlesim simulation by quartus with II verified to achieve the conve
黑金Altera开发板Verilog实例教程
- 控制开发板上的4个LED灯，计数器记到4秒清零，控制LED灯依次亮(Controlling the four leds on the development board, the counter down to the 4 seconds reset, the control the LED light in turn)
计数器
- 计数器,可参数化的计数器，进行M模的计数操作。(Counter, parameterized counter, for M - mode counting operation)