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基于VHDL与CPLD器件的FIR数字滤波器的设计
- 这是我看到的一些资料，希望与大家分享。也许这对您用处不大，但是我的一份诚意。-this is that I see some of the information and hope to share with you all. This may be less useful to you, but my sincerity.
sd_IP
- SD card controller can just read data using 1 bit SD mode. I have written this core for NIOS2 CPU, Cyclone, but I think it can works with other FPGA or CPLD. Better case for this core is SD clock = 20 MHz and CPU clock = 100 MHz (or in the rati
cpld_51_IO
- ]本文介绍了如何利用CPLD(复杂可编程逻辑器件)与单片机的结合实现并行I／ O(输入／输出)接口的扩展。该设计与用8255做并行I／O接口相比，与单片机软件完全兼容， 同时拥有速度快，功耗低，价格便宜，使用灵活等特点-] This article describes how to use the CPLD (complex programmable logic device) and the single-chip combination to achieve parallel I/O
cpld-ppt
- CPLD入门知识，老师的课件！希望可以对大家有所帮助。-CPLD Starter knowledge, the teacher s courseware! I hope we can be helpful.
bit_synch
- 本人写的MSK解调位同步完整程序，基于QuartusII90环境，采用verilog语言编写，程序简练，可靠性高，而且暂用资源少，适合CPLD器件。文件包含仿真和说明，欢迎下载！-I write a complete program MSK demodulation bit synchronization, based on QuartusII90 environment, using verilog language, procedures, concise, high reliability
EPM240ZT100
- The MAX II CPLD has the following features: ■ Low-cost, low-power CPLD ■ Instant-on, non-volatile architecture ■ Standby current as low as 29 μA ■ Provides fast propagation delay and clock-to-output times ■ Provides four global clocks with
fVerrilog_Devr
- 朋友，我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的，现在就将她的Verilog源码也一并贡献给大家：8位优先编码器，乘法器，多路选择器，二进制转BBCD码，加法器，减法器，简简单易懂状态机，四位比较器，7段数码管，i2c总线，lcd液晶LCD显示出来，拨码开关，串口，蜂鸣器，矩阵键盘，跑马灯，交通灯，数字时钟 可直接使用。 -Friends, I Jawen. See previous upload a CPLD Development Board VHDL so
Xilinx-Downloader
- 这是一个Xilinx并口下载线的图纸，可下载Xilinx的CPLD\FPGA,本人试制成功过，并在ISE12.1下载验证。-This is the drawing of a Xilinx parallel port download cable, downloadable Xilinx CPLD \ FPGA, I succeeded in the trial, and in ISE12.1 Download verification.
cpld_config
- This module contains the standard configurations for the CPLD on the Digilab AM188 board. This CPLD implements the i/o port logic for connecting the AM188 bus to the module signals on the interface connectors C1 and C2. This allows access to module p