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ddr_ctrlv
- ddr ram controller vhdl code
DDR_allegro
- 用allegro画的ddr存储器电路。六层板设计，很好的参考资料-Allegro painting with ddr memory circuit. Six-storey plate design, very good reference
testbench
- ddr sdram controller datd module source code
mem-ctrl-rtl
- 实现对ddr的控制，可以在fpga的仿真环境下跑程序，并有testbench可以参考-implement ddr control
DDR-SDRAM
- ddr sdram 控制器的源代码，内有vhdl和verilog。-DDR SDRAM controller
treff-ddr-sdrh
- 本程序源码是DDR SDRAM控制器的VHDL程序源源码，由ALTERA 提供 -The program source code is DDR SDRAM controller VHDL source source code provided by ALTERA
DDR3_DD12
- DRR3 peripheral test for Microblaze processor on Spartan-6