搜索资源列表
rs-codec-8-16
- 这是一个rs译码器的verilog程序运行于quatus-This is a rs decoder running on Verilog quatus
manydecoders_V
- 各种解码译码电路模型的VerilogHDL描述-various decoder decoding circuit model of Verilog HDL descr iption
2_to_4_decoder
- a 2_to_4 decoder example in verilog.
decoder
- this code for a 2 by 4 decoder using verilog-this is code for a 2 by 4 decoder using verilog
RS(204.188)design
- RS(204,188)译码器说明 原文件： rs_decoder.v（顶层文件）, SyndromeCalc.v（计算伴随式）, BM_KES.v（BM求解关键方程）, Forney.v（Forney算法求误差样值）, CheinSearch.v（搜索错误位置）,ff_mul.v（有限域乘法）。 ROM及初始化文件： rom_inv.v（求逆运算）, rom_power.v（求幂运算）； rom_inv.mif（ROM初始化文件）, rom_po
adpcm-and-ppt
- 包括adpcm的简单讲义 adpcm解码Verilog代码 adpcm编码代码-Including handouts adpcm decoder adpcm simple Verilog code for adpcm coding code
ptos
- 16位并行转串行译码器Verilog，以及synopsis综合结果，行为级、门级网单，均已通过仿真验证-16bit parallel to serial decoder and aynthesis result
seven_seg_decoder
- ITS A verilog HDL code for seven segment display .. on different FPGA there are seven segment displays available .. any number from 0 to 9 can be displayed on it .. using this decoder a BCD input is required .. that would be decoded to seven segment
binary_to_bcd
- this a verilog code .. it converts 9 bit integer value to its corresponding twelve bit BCD number that is required as an input to a seven segment decoder or otherwise also an integer that may be represented by binary bits can be changed to its corres
H6502
- H.264标准解码器全部verilog源码，包括帧内、帧间、变换编码、熵编码、滤波等所有模块和著名的6502的软件源码-The standard H.264 decoder all verilog source code, including the frame, frame, transform coding, entropy coding, filtering all modules and the famous 6502' s software source code
project
- arise instruction decoder verilog source code
binary_to_BCD
- 将二进制码转换成BCD码，在verilog环境下可以封装为译码器-BCD code into the binary code in verilog environment is encapsulated as decoder
haiming
- 信息论与编码中，实现的一个简单的（7,4）系统线性分组码，也即海明码-Construct a systematic (7,4) linear block code.You can use c lauguage or HDL (VHDL or Verilog-HDL) to describe it. Construct a linear block decoder,and decode the received code vector[0 1 0 1 1 0 1].Please write the
Mstateei
- 米勒解码器的状态转换模块。用verilog语言编写写，ISE为开发环境 ，经测试可直接使用。 -Miller decoder state transition module. Verilog language writing, ISE development environment has been tested and can be used directly.
rs_encoder_decoder
- RS编解码源程序，有详细的VERILOG程序，用于纠错-RS encoder and decoder
code_83
- 3-8译码器的verilog程序实现-3-8 decoder verilog program ..............
RS_dec
- rs（204,188）译码器，verilog实现，乘法器采用比特异或方式实现-rs (204,188) decoder, verilog achieve multiplier used than specific or way
des.tar
- DES Encoder and Decoder Verilog RTL Code
qiduanyimaqi_verilog
- 七段译码器的verilog实现。VHDL，单片机开发程序，数字逻辑与处理器基础实验，你懂d。-Seven segment decoder verilog implementation. VHDL, MCU development program, the digital logic and processor basic experiment, you know d.
anc dec
- encoder,decoder,testbench and run files