I2C总线协议，可以在quartus上仿真综合，通用性比较好-I2C bus protocol, the simulation can be integrated in quartus, better versatility

quartus的几个IP核（PWWM,RAM,I2C） -quartus several IP cores (PWWM, RAM, I2C)

This details an I2C master component for single master buses, written in VHDL for use in CPLDs and FPGAs. The component reads and writes to user logic over a parallel interface. It was designed using Quartus II, version 11.1. -This details an I2C mas