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ddr_ctrlv
- ddr ram controller vhdl code
control
- Turbo码编码器时序控制模块，能够对于RAM，ROM读写以及编码器其他功能模块的使能进行控制-Turbo code encoder timing control module, to the RAM, ROM reader and encoder modules, other functions can be controlled so that
interleaver
- This is a convolutional interleaver code written in verilog, the ram is sram with ram_ncs, ram_nwe, ram_noe characters.
RAM
- Code for designing 16 bit RAM
ram
- 代码实现了一个由32位寄存器组成的寄存器组，并有多个控制输入和两个输出，方便使用。-The code implements a 32-bit register consisting of registers, and there are multiple control inputs and two outputs, easy to use.
S_ram
- This is code of static ram in vhdl