搜索资源列表
FFT16
- 基于FPGA的16点FFT快速傅立叶变换的Verilog源代码。-the FFT implement of Verilog based on FPGA
clock2001
- 时钟模块之一：二进制转BCD码verilog源代码FPGA advantage编程环境-clock module : BCD switch binary source code Verilog FPGA advantage programming environment
ATA_source_code
- ata控制器verilog源代码，入门的不错参考
EHERNETIPcore
- 该文件包含以太网IP核的相关代码，一共包含24个VERILOG源代码
simplecpu
- 一个16位简单CPU的Verilog源代码。
I2Cdesign.rar
- I2C总线Verilog源代码描述，ModelSim仿真,I2C bus Verilog source code descr iption, ModelSim Simulation
bcd.rar
- vhdl编写的将二进制转BCD码的程序.直接源代码，适合新手编程，语法学习,BCD
comparator.rar
- 一个verilog源代码，作用是比较器的实验程序。,A verilog source code, the role of the experimental procedures comparator.
RISC_8.rar
- 经过验证的8位RISC-CPU源代码，verilog代码，附：汇编测试源代码，而且测试通过。,Verified 8 RISC-CPU source code, verilog code, attached: the compilation of the test source code, and test.
sdh
- SDH是现代光纤通信中广泛应用的数据传输格式,在SDH帧结构中，前9列为开销字节，它包含了很多重要的信息，本程序为SDH开销的接收处理，查找帧头，分频，勤务话字节E1异步fifo。可拆为三段源代码，不知道能不能抵三个程序-SDH is a modern optical fiber communication is widely used in data transmission format, in the SDH frame structure, as the former 9 overhea
YUV2RGB
- 关于YUV转RGB的verilog源代码、说明文档和modelsin仿真，相信对大家一定有很大的帮助，我费了好长时间才找到的！-YUV to RGB on the verilog source code, documentation and modelsin simulation, we believe that there will be a great help, I spent a good long time to find it!
lcd1602-verilog
- 基于QuartusII的LCD1602-Verilog 源代码，可以直接应用于FPGA开发板。-QuartusII based on the LCD1602-Verilog source code, can be directly applied to FPGA development board.
verilog
- 里面包含了多个verilog源代码例子 包括循环码编解码、加法器等等常用的例子 -Which contains a number of Verilog source code examples include the cyclic code coding and decoding, and so on commonly used adder example
RS_Verilog
- rs编解码的verilog实现源代码，从硬件实现rs的编解码-rs codec to achieve the verilog source code, from the hardware codec rs
my_nor
- verilog 源代码 抑或门的程序很好用-vvv
8BitRISC_CPU(VERILOG)
- 8位risc内核源代码，内有体统框图，较其他详细。适合初学者学习-8-bit risc kernel source code, there are decency diagram, compared with other details. Suitable for beginners to learn
ddr-sdram-verilog-resource
- 描述了ddr_sram的源代码,包括SDRAM的引脚功能介绍和Verilog在modulesim及quartus ii的实现-descr iption the resource code of ddr_sram
20 CAN总线实验
- 基于can总线的，Verilog源代码分享，可以在Z7030芯片开发板进行演示。(Based on the CAN bus, Verilog source code sharing, can be demonstrated in the Z7030 chip development board.)
CY7C68013 Verilog test
- CY7C68013固件程序以及 FPGA测试Verilog程序，源代码(CY7C68013 firmware program FPGA test Verilog program, source code)
spi_masterSPI Master 的Verilog源代码
- 实现SPI主站通信功能,感兴趣的可以下载。(spi master use verilog.)