搜索资源列表
-
0下载：
This is a verilog code used oversampled
clock to implement SPI slave. Also include C code for a ARM processor
as the SPI master-This is a verilog code used oversampled
clock to implement SPI slave
-
-
0下载：
基于FPGA的SPI接口设计，主模式，频率可调，verilog HDL编写-FPGA-based SPI interface design, master mode, adjustable frequency, verilog HDL prepared
-
-
0下载：
spi verilog simulatin model with master -spi verilog simulatin model with master
-
-
0下载：
用Verilog HDL 语言编写的，可在FPGA上实现的SPI总线主端 收发读写模块 -SPI Master Read-Write controller core which was Writted by Verilog HDL based on fpga
-
-
0下载：
此代码是SPI接口的Master的Verilog源代码,能很大程度学习相关算法，解决问题-This code is SPI interface Master of Verilog source code
-
-
0下载：
支持主从模式的、可综合的SPI verilog代码-Supports master and slave mode SPI communication module can be integrated RTL code
-
-
0下载：
SPI master 的verilog源码，具有很好的学习价值。-Master SPI Verilog source code, has a good learning value.
-
-
0下载：
Verilog implementation of an SPI slave interface. Intially targetted for Atlys devkit (Xilinx Spartan-6) controlled by TotalPhase Cheetah USB/SPI adapter
-
-
0下载：
spi 的verilog rtl 代码, 包括整体仿真环境，测试码等(spi master or slave verilog rtl code)
-
-
0下载：
实现SPI主站通信功能,感兴趣的可以下载。(spi master use verilog.)
-
-
0下载：
ADC_Interface
Simple SPI interface for AD7908/AD7918/AD7928 written in verilog HDL
-
