搜索资源列表
aes_inv_cipher_top
- aes ip core, 128 bits
hex-bin-core
- 这里面包含两个小工具，一个是.hex文件转.bin文件工具，另一个是.bin文件转.coe文件。希望对在做工程的同行有帮助。-This is a small tool which includes two, one. Hex file transfer. Bin files tools, the other is. Bin file transfer. Coe file. Want to do engineering counterparts helpful.
E1-FramerDeframer
- E1 Framer/Deframer,E1 framer Deframer core implements CCITT (ITU) recommedations G.704,G.706 and G.732 for 30 channel multiplexed E1 stream at 2.048Mbps rate. Note:This project is part of the OpenStacks initiative at the Telecom Software Laborator
8051_ip_core
- 8051微控制器的ip 核的vhdl源代码,其中包含了相应的测试程序.-8051 micro-controller ip nuclear vhdl source code, which contains the corresponding test procedures.
I2C
- 详细描述了I2C的技术规范 版本号为2.1 是采用VHDL编写I2C的IP核的一本不错的参考资料-A detailed descr iption of the I2C specification version 2.1 is the use of VHDL for the preparation of the IP core I2C a good reference
I2C
- IIC通信协议IP核，描述IIC协议在FPGA上的实现-IIC communications protocol IP core
slaveController
- 对USB的从机设备的IP核进行了重新设计并在一定程度上进行了优化-On the USB device from the IP core has been redesigned to some extent, is optimized
digitaloscilloscope
- This digital oscilloscope takes a MCU and FPGA as the core. We made emphases on the choice of the sampling methods and the implement of equivalent sampling as a result, our design not only has the real-time sampling mode but also can reach the highes
23
- 基于FPGA的液晶显示控制器的设计，FPGA用的是EP2C5,LCD用的是ST7920内核的122*32点阵的LCD，显示中西文字符-FPGA-based LCD display controller design, FPGA is used EP2C5, LCD is used in the ST7920 core of 122* 32 dot matrix LCD, display of Chinese and Western characters
I2CSLAVE
- 已经验证过的I2C，slave的IP，core，从一开源网站下载的，代码写的非常好，节省了FPGA的资源，比起以往的slave的CORE，这个CORE减少了寄存器的使用。-Has been verified I2C, slave of the IP, core, from an open source website, the code is written in a very good save FPGA resources than the previous slave of CORE, t
ac97_latest.tar
- simple AC97 Controller IP core. It supports one AC97 codec, with 6 output and 3 input channels. This AC97 Controller s fully AC97 Revision 2.2 compliant. it only supports AC97 Audio Codecs.
jj
- 本题设计一个数字存储示波器，以Xilinx公司20万门FPGA芯片为核心，辅以必要的外围电路（包括信号调理、采样保持、内部触发、A/D转换、D/A转换和I/O模块），利用VHDL语言编程，实现了任意波形的单次触发、连续触发和存储回放功能，并按要求进行了垂直灵敏度和扫描速度的挡位设置。信号采集时，将外部输入信号经信号调理模块调节到A/D电路输入范围，经A/D转换后送入FPGA内部的双口RAM进行高速缓存，并将结果通过D/A转换送给通用示波器进行显示，完成了对中、低频信号的实时采样和高频信号的等效采
verilog
- source code for USB 2.0 fonction core in verilog
vhdl
- The VGA/LCD core provides elementary VGA capabilities for embedded systems. It supports both CRT and LCD displays, with user programmable resolutions and timings.
vgadriver
- controladpr vga core con test bench
ft2232hcore_latest.tar
- ft2232 IP Core
divider
- a vhdl code for divide operation in fpga spartan6
msp430_cpu_core_vhdl_v01
- VHDL implementation of MSP430 core
MIPI_CSI_2_Rx
- MIPI CSI 2 Rx verilog / vhdl core
MIPI_DSI_Tx
- MIPI DSI Tx verilog / vhdl core