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用VHDL实现查找表方式的FIR滤波器
- 这些是我所看到的一些资料，希望与大家分享。也许对您用处不大，但我是一片诚意-these are what I saw in some of the information and hope to share with you all. Perhaps your little usefulness, but I was a sincerity
基于VHDL与CPLD器件的FIR数字滤波器的设计
- 这是我看到的一些资料，希望与大家分享。也许这对您用处不大，但是我的一份诚意。-this is that I see some of the information and hope to share with you all. This may be less useful to you, but my sincerity.
motorctrl
- 滤波器设计及数据采集系统，希望对你有用，欢迎分享。本人想要VHDL的步进电机控制代码-filter design and data acquisition systems in the hope that useful to you, welcome to share. I want VHDL code stepper motor control
26_1000
- 若干VHDL语言的源代码，我觉得应该用用仅供参考-several VHDL source code, I think that should be used for reference purposes only
canvhdl
- can总线控制器的原代码，是用vhdl写的，我没有验证过，不保证正确性。可以作为参考。 -can Bus Controller's original code is written in vhdl, I have not tested, it does not guarantee accuracy. Can be used as reference.
SojournerProgram
- 这里是我在学校时所写的一些程序，其中有些Java程序可能要重新编译一下才能运行，具体如下：C Course Disign——C语言编写的时钟程序Very Simple CPU——CPU仿真工具StudentQuery——基于SQL语言数据库的学籍管理系统Theory of Computation——一些关于计算理论算法的实现，详见内附说明Hotel——酒店管理系统另外还有一些硬件VHDL方面的程序，整理好后会陆续上传-here at school I wrote some of the proc
sdh
- SDH是现代光纤通信中广泛应用的数据传输格式,在SDH帧结构中，前9列为开销字节，它包含了很多重要的信息，本程序为SDH开销的接收处理，查找帧头，分频，勤务话字节E1异步fifo。可拆为三段源代码，不知道能不能抵三个程序-SDH is a modern optical fiber communication is widely used in data transmission format, in the SDH frame structure, as the former 9 overhea
desingofmultiply
- 设计定点寄存器的好书，希望大家喜欢，对哦多交流-Design of fixed-point register books, I hope you like it, oh, more exchanges of
LIBRARYIEEE
- 简易电子琴 基本代码，不完全，希望有人能补充 -Simple flower basic code, not completely, I hope someone can add
components
- USART coded in VHDL. It is writted in 5 files. I am uploading the files in order.
Lab8
- This codes is one of my univ projects I ve been working on for 3months. I d like to share it and make it work more properly.
VGA_ILOVEYOU
- files describe a example show to vga : "I LOVE YOU"
timing_recovery
- 我对一个输入调制信号：采样率FS=1200K，中心频率F0=300K，带宽300K。输入信号为一个[样点数,2]的矩阵,即I,Q两路. 进行频谱搬移，分为I，Q分量两路进行矢量乘法，NCO的设置为FC=300K，t=样点数乘以1/FS， 乘完以后我的频谱上显示竟然信号带宽增加了300K，但是中心频率没有改变，请问各位朋友是哪儿出了问题？谢谢您的阅读和意见-Digital Down Converter for matlab realized, certain design speci
Sequencedetector
- 序列检测器可用来检测一组或多组由二进制码组成的脉冲序列信号，这在数字通信领域有广泛的应用。当检测器连续收到一组串行二进制码后，若这组码与检测器中预制的码相同，输出为A，否则输出为B。序列检测I/O口的设计如下：设Din是串行数据输入端，clk是工作时钟，clr是复位信号，D是8位待检测预置数，QQ是检测结果输出端。-Sequence detector can be used to detect one or more sets consisting of binary code from the
and_2
- VHDL 与门 ，最基本的学习VHDL的程序，我写的第一个VHDL程序，估计作用不大哦-VHDL and the gate, the basic process of learning VHDL, I am the first to write a VHDL program, estimated that little oh
I2C_SLAVE
- I2C slave端。可支持1带多。本人已经过调试，确认是可用的。-I2C slave side. Can support more than one band. I have been debugging, sure there is available.
jj
- 本题设计一个数字存储示波器，以Xilinx公司20万门FPGA芯片为核心，辅以必要的外围电路（包括信号调理、采样保持、内部触发、A/D转换、D/A转换和I/O模块），利用VHDL语言编程，实现了任意波形的单次触发、连续触发和存储回放功能，并按要求进行了垂直灵敏度和扫描速度的挡位设置。信号采集时，将外部输入信号经信号调理模块调节到A/D电路输入范围，经A/D转换后送入FPGA内部的双口RAM进行高速缓存，并将结果通过D/A转换送给通用示波器进行显示，完成了对中、低频信号的实时采样和高频信号的等效采
intit
- 初始化网络芯片，我负责的是MAC的初始化和PHY初始化。可以试着在此基础上编写以太网。-Initialize the network chip, I am responsible for the MAC and PHY initialization initialization. Can try to write on this basis Ethernet.
vhdl-code-64-bit-vedic
- i hope this will help for u
test_sd8_ychdj1280000
- fpga 开发，主要是针对nios核的一些开发，希望大家能相互的交流交流。(FPGA development, mainly for the development of some of the NIOS kernel, I hope we can exchange and exchange with each other)