搜索资源列表
Canny
- 首先利用C实现了一个图像边缘提取的算法，然后利用vivado高层次综合，将其综合为verilog代码。-First, the use of C implements a image edge extraction algorithm, then use vivado high-level synthesis, as its comprehensive verilog code.
bit2dec_fft
- bit to dec 并对数据进行FFT变换，配合xilinx Vivado采数使用。-and the data bit to dec FFT transform, with the number of use xilinx Vivado mining.
sin_wave
- 在vivado开发环境下，调用ram IP，实现可调频的正弦波信号发生器。-vivado IP signal generator
xadc
- 基于xinlinx的vivado的xadc设计代码-Based on the xinlinx vivado xadc design code
7_VGA
- VGA屏幕上显示出白-红-绿-蓝的彩条信号。基于basys3，软件平台vivado-VGA screen display color signal of white- red green blue. Based on basys3 software platform, vivado
2_digital_clock
- 采用Verilog HDL RTL 描述完成数字钟，基于basys3，软件平台：vivado-Using Verilog HDL RTL to complete the descr iption of digital clock based on basys3 software platform: vivado
5_bluetooth_uart
- 基于FPGA，硬件平台：basys3，软件平台：vivado。描述语言：verilog。封装自己的蓝牙串口IP。蓝牙串口数据传输需要三个模块，分别是波特率生成模块，接收模块和发送模块。-Based on the FPGA hardware platform, software platform: basys3, vivado. Descr iption: verilog. Package your own Bluetooth serial port IP. Bluetooth serial da
6_XADC
- 基于FPGA，硬件平台：basys3，软件平台：vivado。描述语言：verilog。 实现XADC采集双路外部电压输入。-Based on the FPGA hardware platform, software platform: basys3, vivado. Descr iption: verilog. The implementation of XADC acquisition dual external voltage input.
vivado.2015.4.1.win64
- Vivado 2015.4 破解+License-Vivado 2015.4 Crack and License
fir_vivado
- 此压缩包里面有基于vivado平台的工程，包括了正弦信号的产生，还有fir滤波器的设计以及fft算法的设计实现-in this package,there are three projects of the generation of the signal of sin and the design of fir filter and the ari
cos_test
- 该段代码是产生正弦信号的一个测试代码，能够基于vivado这个平台产生正弦信号-this code is the generation of the signal of sin base on the platform of vivado
VivadoLicense
- Vivado liscenses for the software
ug908-vivado-programming-debugging
- ug908-vivado-programming-debugging(ug908vivadoprogrammingdebugging)
vivado简明教程
- vivado的入门教程，从工程创建到简单的系统搭建，以及sim仿真，都详细的以图片的形式给出，适合初学者(Vivado tutorial, from engineering creation to simple system building, and sim simulation, are detailed in the form of pictures given, suitable for beginners)
lab1 Vivado Design Flow
- 适用于对verilog语言的初步学习，本文本就对RTL的编写，功能仿真，实现，布线，综合，以及生成比特流等环节进行了初步的描述。适合初学者学习。(For the preliminary study of Verilog language)
vivado 2017.1破解版
- Xilinx Vivado 2017.1破解版百度网盘下载地址(Xilinx Vivado 2017.1 crack baiduyun download link)
dma_performance_demo
- 含全套PCIE调试文件：FPGA代码（Verilog），驱动文件及安装（包含Windows和Linux）(PCI_Express Vivado Windows Driver)
Lab 1
- FPGA XILINX VIVADO LAB
TFG_Comparativa_Deteccio_Cares
- 使用zynq去使用opencv，使用C++语言，编译器使用的vivado 2016，英文原版的，需要读者去自己翻译。(Use zynq to use opencv, use the C++ language, the compiler uses vivado 2016, the original English version, and requires readers to translate themselves.)
vivado 2018 license
- Vivado Design Suite HLx 2018.1 xilinx_vivado_2018_license Xilinx_Vivado_SDK_2018.1