用数字锁相环实现位同步信号提取，包含各个模块的电路设计程序。-To achieve bit synchronization with digital phase-locked loop signal extraction, each module contains the circuit design process.

基于fpga的位同步信号提取仿真 使用vhdl语言 quartus-To use vhdl language quartus fpga bit synchronization signal extraction-based simulation