搜索资源列表
pli_handbook_examples_pc
- pli_handbook_examples_pc verilog hdl 与C的接口的典型例子-pli_handbook_examples_pc verilog and C hdl The classic example of the interface
CLOCK_co-design_of_C_and_Verilog
- A clock writing by Verilog which can count from 00:00 to 23:59. With a C file to see the simulation results. A co-design example of C and Verilog.
Find_medium_value_co-design_of_C_and_Verilog
- A code writing by Verilog which can find medium value. With a C file to see the simulation results. A co-design example of C and Verilog.
RGB_color_transform_gray_level_co-design_of_C_and_
- to use verilog code and c to translate a RGB bmp image(512*512) to a gray level image
show_your_student_ID_number_co-design_of_C_and_Ver
- As the source code name, this code is writing in Verilog and also inside the folder there is a c code to see the simulation results from verilog.
Traffic_sign_co-design_of_C_and_Verilog
- This is an extension of sign example. You can design your own traffic sign by using Verilog. And the result from Verilog can be seen by the attached C file.