用Verilog实现卷积码（2，1，2）的编码器，采用状态机来完成在modelsim下的仿真-Verilog implementation using convolution code (2,1,2) encoder, using a state machine to complete the modelsim simulation under the

第三届中兴捧月进入总决赛作品分布式基站设备仿真系统，有2部分完整的源代码-Third ZTE holding the Finals works to distributed base station equipment simulation system, part of the complete source code