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howtoOpmizetheM25P80
- M25P80是意法半导体公司推出的8M大容量串行接口Flash器件，采用2.7V-3.6V单电源供电，兼容标准的SPI接口，器件在上升沿接收数据，在下降沿发送数据，接口时钟最高为40MHz，支持最大256bytes的快速页面编程操作、快速的块擦除（512Kbit）操作和快速的整体擦除操作具有操作暂停和硬件写保护功能-M25P80 is agreed that the semiconductor company introduced 8M large capacity Serial Interfa
ForRCTTH
- 电子钟电脑校正时间程序 （主要演示Vc环境下，串口可靠操作及相关通讯协议，完整代码，内有封装串口读写类，自主开发，并附开发说明文档）-Electronic clock computer correction time program (The main demo Vc environment, serial reliable operation and related communication protocols, complete code, with the package ser
clock
- 这个程序的主要内容是基于VHDl的时钟方面的编程设计-The main content of this program is based VHDl clock programming design
SDRAM50M
- 黑金开发板上基于芯片FPGAEP4CE15F17C8N中SDRAM，我自己编写的Verilog程序。时钟设定的是50M，希望可以帮到大家。-Black gold development board based on SDRAM chip FPGAEP4CE15F17C8N, my own writing Verilog program the clock setting is 50 m, the hope can help you
SDRAM100M
- 黑金开发板上基于芯片FPGAEP4CE15F17C8N中SDRAM，我自己编写的Verilog程序。时钟设定的是100M，希望可以帮到大家。-Black gold development board based on SDRAM chip FPGAEP4CE15F17C8N, my own writing Verilog program the clock setting is 100m, the hope can help you
exercise3
- 用verilog实现dsp与Fpga接口的同步设计，其功能包括读写操作及四个功能模块，采用两个fifo实现不同时钟域的地址与数据的转换，在quartus ii11.0环境下运行，运行此程序之前需运行将调用fifo。-Dsp using verilog achieve synchronization with Fpga interface design, its features include read and write operations and four functional modul