clock synchronization coding in MATLAB

用verilog实现dsp与Fpga接口的同步设计，其功能包括读写操作及四个功能模块，采用两个fifo实现不同时钟域的地址与数据的转换，在quartus ii11.0环境下运行，运行此程序之前需运行将调用fifo。-Dsp using verilog achieve synchronization with Fpga interface design, its features include read and write operations and four functional modul

16QAM调制数据，符号速率1Mbps，用于时钟同步电路的输入数据。-16QAM modulation data, symbol rate 1Mbps, for clock synchronization circuit input data.