搜索资源列表
crc上传程序
- 写CRC编解码程序时，整理的文件，压缩文件既有理论说明，也有源代码。源代码格式用C,VHDL,Verilog。-write CRC codec procedures, collating documents, compressed files both theoretical statements, and the active code. Source code format C, VHDL, Verilog.
伪随机序列
- 线形反馈移位寄存器（LFSR)是数字系统中一个重要的结构，本程序可以自动产生AHDL,VHDL,Verilog的源代码及电路原理图。程序可以运行在win98/2000/NT平台-linear feedback shift register (LFSR) digital system is an important structure, the process can be automatically generated AHDL, VHDL, Verilog source code and ci
asyn_receiver
- 带奇偶校验位的串口接收的Verilog源代码-failed to translate
C6474L_EVM_RTL
- TI C6474评估板的fpga源代码，初始化板子必备代码，Verilog HDL硬件语言编写。-TI C6474 evaluation board fpga source code, the code necessary to initialize the board, Verilog HDL hardware language.
uart2bus_latest.tar
- 这是一个用Verilog HDL和VHDL设计的UART控制器的IP核，里面有详细的源代码-This is a Verilog HDL and VHDL design UART controller IP core, which has detailed source code
4NandFlash.tar
- nandflash接口的verilog代码，用verilog编写，片上系统SOC源代码分析的nandflash接口代码，总线是wishbone-Nandflash u63A5 u53E3 u7684verilog u4EE3 u7801 uFF0C u7528verilog u7F16 u5199 uFF0C u7247 u4E0A u7CFB u7EDFSOC u6E90 u4EE3 u7801 u5206 u6790 u7684nandflash u
5SDRAM.tar
- SRAM接口的verilog代码，用verilog编写，片上系统SOC源代码分析的SRAM接口代码，总线是wishbone-SRAM u63A5 u53E3 u7684verilog u4EE3 u7801 uFF0C u7528verilog u7F16 u5199 uFF0C u7247 u4E0A u7CFB u7EDFSOC u6E90 u4EE3 u7801 u5206 u6790 u7684SRAM u63A5 u53E3 u4EE3
6IIS.tar
- IIS接口的verilog代码，用verilog编写，片上系统SOC源代码分析的IIS接口代码，总线是wishbone-IIS interface verilog code