C实现模拟与或非门的逻辑电路，可以多元件输入，支持元件延时，可以绘制输出波形-C simulation and implementation of logic circuits or door, you can enter many components to support the delay components, you can draw the output waveform

verilog 门级设计及仿真标准单元库，包含142个基本的逻辑门单元。可用于VERILOG开发实现与或非、加法、减法、累加等基本的逻辑运算单元，实现精确的逻辑仿真。-verilog gate-level design and simulation of a standard cell library contains 142 basic logic gate unit. VERILOG implementation and can be used to develop or, addition