带溢出的四位补码加法运算verilog代码-verilog

模为 60 的 BCD码加法计数器，采用verilog语言编写。-BCD code module for the addition of 60 counters, using verilog language.

2个整数的加法运算，有verilog语言编写-Two integer addition operation

verilog 门级设计及仿真标准单元库，包含142个基本的逻辑门单元。可用于VERILOG开发实现与或非、加法、减法、累加等基本的逻辑运算单元，实现精确的逻辑仿真。-verilog gate-level design and simulation of a standard cell library contains 142 basic logic gate unit. VERILOG implementation and can be used to develop or, addition

用verilog语言实现15进制加法计数器的功能-Achieve 15 binary adder counter function using verilog language