搜索资源列表
adder
- 基本组合电路 含异步清零和同步时钟的加法计数器-Basic combinational circuits with asynchronous clear and the addition of synchronous clock counter
bcd60counter
- 同步的60进制计数器 均用四位二进制表示-60 synchronous binary counter with four binary
fifo-code
- Verilog代码：同步\异步FIFO。包含格雷码计数器.-Verilog code: syncronous\asyncourous FIFO. containing gray counter.
code
- 基于Verilog HDL 1、div为分频模块,晶振50M,目的是得到1HZ 2、cnt为异步清零，同步加载，同步使能的十二进制计数器。-4-Bit Binary Up Counter with Asynchronous Clear, Synchronous Load, and Asynchronous En.
Counter
- 两种方法实现的同步计数器 （包括例化的），提供全部代码。-Synchronous counter in two ways (including the example of), provided all the code.
counter
- verilog 写的一个增减计数器的例子，可用于位同步时钟提取中，已经经过验证，可直接添加到自己的工程中。-Verilog write an increase or decrease the counter example, can be used to extract a synchronous clock, has been validated and can be directly added to your project.
shiyan2
- 含异步清0和同步时钟使能的加法计数器的设计，可以从0加到99，使用VHDL语言-Cleared containing asynchronous and synchronous clock enable the addition of counter design, added to 99 can range 0, the use of VHDL language
kebenchengxu
- VHDL代码，一些课本的小程序。包含3线-8线译码器，4选1选择器，6层电梯，8线-3线编码器，8线-3线优先编码器，8选1，BCD-7段显示译码器真值表，半加器，摩尔状态机，数字频率计，数字时钟，同步计数器，序列检测器的设计，序列信号发生器，一般状态机等等。(The small program of some textbooks. Includes 3 -8 decoder, 4 1 selector, 6 elevator, line 8 Line 8 line -3 encoder, -3
counter4b
- Vivado同步计数器VHDL设计 具有异步复位和同步预置数功能 同步计数器同步计数器同步计数器(The Vivado synchronous counter VHDL is designed with asynchronous reset and synchronous preset function, synchronous counter, synchronous counter and synchronous counter.)