搜索资源列表
xugc
- cic512 5阶cic滤波器，抽取12倍，的verilog程序，已经通过仿真验证 -5CIC
cic_dec_14_three_2
- 2倍抽取14位的3级CIC滤波器的FPGA实现的verilog代码-cic filter
fir
- fir滤波器的几种结构virelog代码（串行，并行，DA结构以及多相抽取结构），程序包为ise工程-fir filter several the structure virelog code (serial, parallel, DA structure and multiphase extraction structure), the program package for the ise project
decifilter256
- sigma-delta 256倍数字抽取滤波器的matlab设计-matlab design of sigma-delta 256 digital decimation filter
polyfilter
- 用verilog实现一个四阶的多项抽取滤波器，实现2倍下采样-Number of decimation filter verilog to achieve a fourth order 2 times sampling
cic_dec_8_three
- 用verilog语言实现一个3级、抽取率为2的8位hogenauer CIC抽取滤波器-Verilog language to achieve a 3, the extraction rate of 8 hogenauer CIC decimation filter
CIC_Compensation_Filter_Coefficients
- CIC补偿滤波器设计源代码，包含量化功能，可以作为FPGA开发滤波器设计数据。适用于CIC抽取和CIC插值滤波器的补偿滤波器应用。-CIC compensation filter design source code, including the quantization function can be used as a the FPGA development filter design data. Apply to CIC decimation filter compensation an
CIC
- 抽取滤波器,实现512倍抽取2级CIC滤波器，抗混叠滤波以及抽取作用！-cic filter
cic
- CIC Filter 实现的matlab源码.里面使用MATLAB，verilog，c++混合实现CIC抽取滤波器-CIC Filter achieve matlab source. Inside using MATLAB, verilog, c++ hybrid implementation CIC decimation filter
12312312
- 半带滤波器原理与设计 一种抽取因子为2的FIR滤波器.pdf(the concept of half bank filter)